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PENTIUM(R) III XEONTM PROCESSOR AT 700 MHz and 900 MHz.
Datasheet Product Features
Binary compatible with applications running on previous members of the Intel microprocessor family Optimized for 32-bit applications running on advanced 32-bit operating systems Dynamic Independent Bus architecture: separate dedicated external 100 MHz System Bus and dedicated internal cache bus operating at full processor core speed Power Management capabilities System Management mode Multiple low-power states Single Edge Contact (S.E.C.) cartridge packaging technology; the S.E.C. cartridge delivers high performance processing and bus technology to mid range to high end servers and workstations 100 MHz system bus speeds data transfer between the processor and the system Integrated high performance16k instruction and 16k data, nonblocking, level-one cache Available in 1MB (700 MHz) or 2MB (900 MHz and 700 MHz) unified, non-blocking level-two cache Enables systems which are scaleable up to two processors and 64GB of physical memory SMBus interface to advanced manageability features Streaming SIMD Extensions for enhanced video, sound and 3D performance
The Intel(R) Pentium(R) III XeonTM Processor at 700 MHz with 1MB or 2MB L2 cache and 900 MHz with 2MB L2 cache is designed for mid-range to high-end servers and workstations, and is binary compatible with previous Intel(R) Architecture processors. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz provides the best performance available for applications running on advanced operating systems such as Microsoft* Windows* 98, Microsoft* Windows* NT*, and UNIX*. The processor is scalable to four processors in a multiprocessor system and extends the power of the Pentium(R) Pro processor with new features designed to make this processor the right choice for powerful workstation, advanced server management, and missioncritical applications. Pentium(R) III XeonTM processor at 700 MHz and 900 MHz-based workstations offer the memory architecture required by the most demanding workstation applications and workloads. Specific features of the processor address platform manageability to meet the needs of a robust IT environment, maximize system up time and ensure optimal configuration and operation of servers. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz enhances the ability of server platforms to monitor, protect, and service the processor and its environment.
Order Number: 248711-002 March 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) Pentium(R) III XeonTM processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 *Other names and brands may be claimed as the property of others.. Copyright (c) 2001, Intel Corporation
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TABLE OF CONTENTS
TABLE OF CONTENTS
PRODUCT FEATURES............................................................................................................ I
1. INTRODUCTION ......................................................................................................................... 6 2. TERMINOLOGY .......................................................................................................................... 7 2.1 S.E.C. CARTRIDGE TERMINOLOGY.................................................................................... 7 2.2 STATE OF DATA ................................................................................................................ 8 2.3 REFERENCES.................................................................................................................... 8 3. ELECTRICAL SPECIFICATIONS ............................................................................................... 9 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.2 3.5 3.6 3.7 3.7.2 3.8 3.9 3.10 3.11 3.12 SYSTEM BUS AND VREF................................................................................................... 9 POWER AND GROUND PINS ............................................................................................... 9 DECOUPLING GUIDELINES ............................................................................................... 11 VCC_CORE ................................................................................................................... 11 LEVEL 2 CACHE DECOUPLING............................................................................. 11 SYSTEM BUS AGTL+ DECOUPLING..................................................................... 11 CLOCK FREQUENCIES AND SYSTEM BUS CLOCK RATIOS .................................................. 11 MIXING PROCESSORS OF DIFFERENT FREQUENCIES ................................... 13 VOLTAGE IDENTIFICATION................................................................................................ 13 SYSTEM BUS UNUSED PINS AND TEST PINS ..................................................................... 16 SYSTEM BUS SIGNAL GROUPS ........................................................................................ 16 ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS ............ 17 ACCESS PORT (TAP) CONNECTION................................................................................. 17 MAXIMUM RATINGS ......................................................................................................... 18 PROCESSOR DC SPECIFICATIONS ................................................................................... 18 AGTL+ SYSTEM BUS SPECIFICATIONS ............................................................................ 22 SYSTEM BUS AC SPECIFICATIONS................................................................................... 24
4. SIGNAL QUALITY..................................................................................................................... 33 4.1 BUS CLOCK SIGNAL QUALITY SPECIFICATIONS ......................................................................... 33 4.2 AGTL+ SIGNAL QUALITY SPECIFICATIONS....................................................................... 34 4.2.2 AGTL+ Signal Quality Specifications .............................................................................. 34 4.2.3 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES ............................................ 34 4.3 NON-GTL+ SIGNAL QUALITY SPECIFICATIONS.......................................................................... 37 4.3.1 2.5V Signal Overshoot/Undershoot Guidelines ............................................................. 38 4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications ........................................ 39 4.3.3 Measuring BCLK Overshoot/Undershoot........................................................................ 39 4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION ............................................ 40 4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE............................................ 40 5. PROCESSOR FEATURES........................................................................................................ 41 5.1 LOW POWER STATES AND CLOCK CONTROL............................................................................. 41 5.1.1 NORMAL STATE -- STATE 1 ................................................................................. 41 5.1.2 AUTO HALT POWER DOWN STATE -- STATE 2 ................................................. 41
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TABLE OF CONTENTS 5.1.3 STOP-GRANT STATE -- STATE 3......................................................................... 42 5.1.4 HALT/GRANT SNOOP STATE -- STATE 4 ........................................................... 42 5.1.5 SLEEP STATE -- STATE 5..................................................................................... 43 5.1.6 CLOCK CONTROL .................................................................................................. 43 5.2 SYSTEM MANAGEMENT BUS (SMBUS) INTERFACE ........................................................... 43 5.2.1 PROCESSOR INFORMATION ROM....................................................................... 44 5.2.2 SCRATCH EEPROM ............................................................................................... 48 5.2.3 PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS ....................................................................................................... 48 5.2.4 THERMAL SENSOR ................................................................................................ 49 5.2.5 THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS ............................. 50 5.2.6 THERMAL SENSOR REGISTERS .......................................................................... 51 5.2.7 SMBus Device Addressing....................................................................................... 53 6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS......................................... 55 6.1 THERMAL SPECIFICATIONS .............................................................................................. 55 6.1.1 POWER DISSIPATION ............................................................................................ 55 6.1.2 PLATE FLATNESS SPECIFICATION...................................................................... 57 6.2 PROCESSOR THERMAL ANALYSIS .................................................................................... 57 6.2.1 THERMAL SOLUTION PERFORMANCE ............................................................... 57 6.2.2 THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE............. 58 6.2.3 MEASUREMENTS FOR THERMAL SPECIFICATIONS......................................... 58 7. MECHANICAL SPECIFICATIONS ........................................................................................... 60 7.1 WEIGHT .................................................................................................................................. 64 7.2 CARTRIDGE TO CONNECTOR MATING DETAILS.......................................................................... 64 7.3 SUBSTRATE EDGE FINGER SIGNAL LISTING ............................................................................. 66 8. INTEGRATION TOOLS............................................................................................................. 76 8.1 IN-TARGET PROBE (ITP).......................................................................................................... 76 8.1.1 PRIMARY FUNCTION .................................................................................................... 76 8.1.2 DEBUG PORT CONNECTOR DESCRIPTION .............................................................. 76 8.1.3 KEEP OUT CONCERNS ................................................................................................ 77 8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS................................ 77 8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS ...................................................................... 77 8.1.6 DEBUG PORT SIGNAL NOTES..................................................................................... 80 8.1.7 Using the TAP to Communicate to the processor........................................................... 82 8.2 LOGIC ANALYZER INTERCONNECT (LAI) AND TRACE CAPTURE TOOL CONSIDERATIONS.............. 82 8.2.1 LAI and Trace Capture Tool System Design Considerations ......................................... 82 8.2.2 LAI and Trace Capture tool Mechanical Keep Outs ....................................................... 82 9. BOXED PROCESSOR SPECIFICATIONS............................................................................... 83 9.1 INTRODUCTION ........................................................................................................................ 83 9.2 MECHANICAL SPECIFICATIONS ................................................................................................. 83 9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS ........................................................ 85 9.2.2 BOXED PROCESSOR HEATSINK WEIGHT ................................................................. 85 9.2.3 BOXED PROCESSOR RETENTION MECHANISM ...................................................... 85 9.3 THERMAL SPECIFICATIONS....................................................................................................... 86 9.3.1 Boxed Processor Cooling Requirements ........................................................................ 86 9.3.2 Boxed Processor Passive Heatsink Performance .......................................................... 86 9.3.2 Optional auxiliary fan attachment.................................................................................... 87 10. APPENDIX............................................................................................................................... 90
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TABLE OF CONTENTS 10.1 ALPHABETICAL SIGNALS REFERENCE ..................................................................................... 90 10.1.1 A[35:03]# (I/O)............................................................................................................... 90 10.1.2 A20M# (I) ...................................................................................................................... 90 10.1.3 ADS# (I/O)..................................................................................................................... 90 10.1.4 AERR# (I/O) .................................................................................................................. 90 10.1.5 AP[1:0]# (I/O) ................................................................................................................ 90 10.1.6 BCLK (I)......................................................................................................................... 90 10.1.7 BERR# (I/O) .................................................................................................................. 91 10.1.8 BINIT# (I/O) ................................................................................................................... 91 10.1.9 BNR# (I/O) .................................................................................................................... 91 10.1.10 BP[3:2]# (I/O) .............................................................................................................. 91 10.1.11 BPM[1:0]# (I/O) ........................................................................................................... 91 10.1.12 BPRI# (I) ..................................................................................................................... 91 10.1.13 BR0# (I/O), BR[3:1]# (I)............................................................................................... 91 10.1.15 CORE_AN_SENSE (O) .............................................................................................. 92 10.1.16 D[63:00]# (I/O) ............................................................................................................ 92 10.1.17 DBSY# (I/O) ................................................................................................................ 93 10.1.18 DEFER# (I).................................................................................................................. 93 10.1.19 DEP[7:0]# (I/O)............................................................................................................ 93 10.1.20 DRDY# (I/O) ................................................................................................................ 93 10.1.21 FERR# (O) .................................................................................................................. 93 10.1.22 FLUSH# (I) .................................................................................................................. 93 10.1.23 HIT# (I/O), HITM# (I/O) ............................................................................................... 93 10.1.24 HV_EN# (O) ................................................................................................................ 93 10.1.25 IERR# (O) ................................................................................................................... 93 10.1.26 IGNNE# (I) .................................................................................................................. 94 10.1.27 INIT# (I) ....................................................................................................................... 94 10.1.28 INTR - see LINT[0] ...................................................................................................... 94 10.1.29 LINT[1:0] (I) ................................................................................................................. 94 10.1.30 LOCK# (I/O) ................................................................................................................ 94 10.1.31 L2_SENSE ................................................................................................................. 95 10.1.32 OCVR_EN (I) .............................................................................................................. 95 10.1.33 OCVR_OK(O) ............................................................................................................. 95 10.1.34 NMI - See LINT[1] ....................................................................................................... 95 10.1.35 PICCLK (I) ................................................................................................................... 95 10.1.36 PICD[1:0] (I/O) ............................................................................................................ 95 10.1.37 PRDY# (O) .................................................................................................................. 95 10.1.38 PREQ# (I).................................................................................................................... 95 10.1.39 PWREN[1:0] (I) ........................................................................................................... 95 10.1.40 PWRGOOD (I) ............................................................................................................ 95 10.1.41 REQ[4:0]# (I/O) ........................................................................................................... 97 10.1.42 RESET# (I) .................................................................................................................. 98 10.1.43 RP# (I/O) ..................................................................................................................... 98 10.1.44 RS[2:0]# (I) .................................................................................................................. 98 10.1.45 RSP# (I) ...................................................................................................................... 98 10.1.46 SA[2:0] (I) .................................................................................................................... 98 10.1.47 SELFSB0 (I) SELFSB1 (O) ......................................................................................... 99 10.1.48 SLP# (I) ..................................................................................................................... 100 10.1.49 SMBALERT# (O)....................................................................................................... 100 10.1.50 SMBCLK (I) ............................................................................................................... 100 10.1.51 SMBDAT (I/O) ........................................................................................................... 101 10.1.52 SMI# (I) ..................................................................................................................... 101 10.1.53 STPCLK# (I) .............................................................................................................. 101 10.1.54 TCK (I)....................................................................................................................... 101
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TABLE OF CONTENTS 10.1.55 TDI (I) ........................................................................................................................ 101 10.1.56 TDO (O) .................................................................................................................... 101 10.1.57 TEST_2.5_[A23, A62, B27] (I) .................................................................................. 101 10.1.58 THERMTRIP# (O) ..................................................................................................... 101 10.1.59 TMS (I) ...................................................................................................................... 101 10.1.60 TRDY# (I) .................................................................................................................. 102 10.1.61 TRST# (I) .................................................................................................................. 102 10.1.62 VID_L2[4:0], VID_CORE[4:0] (O) ............................................................................. 102 10.1.63 VIN_SENSE .............................................................................................................. 102 10.1.64 WP (I) ........................................................................................................................ 102 10.2 SIGNAL SUMMARIES ............................................................................................................ 102
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INTRODUCTION
1. INTRODUCTION
The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz, like the Pentium(R) Pro, Pentium(R) II, Pentium(R) II XeonTM and previous Pentium(R) III XeonTM processors, implements a Dynamic Execution micro-architecture, a unique combination of multiple branch prediction, data flow analysis, and speculative execution. The Pentium(R) III XeonTM processor at 700 MHz will be available in 1MB and 2MB L2 cache sizes whereas the Pentium(R) III XeonTM processor at 900 MHz will only be available in the 2MB L2 cache size. The Pentium(R) III XeonTM processor improves upon previous generations of Intel(R) processors by adding Streaming SIMD Extensions. The Single Instruction Multiple Data (SIMD) extensions significantly accelerate performance of 3D graphics. Besides 3D graphics improvements, the extensions also include additional integer and cacheability instructions that improve other aspects of performance. In addition, the Pentium(R) III XeonTM processor utilizes a variation of the S.E.C. (Single Edge Contact) package technology first introduced on the Pentium(R) II processor. The SEC packaging technology allows the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz to implement the Dual Independent Bus Architecture and have up to 2MB of level 2 cache. The level 2 cache is integrated in the processing unit and communication occurs at the full speed of the processor core. As with previous members of the Pentium(R) II XeonTM processor family, the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz features built-in direct multiprocessing support. For systems with up to four processors, it is important to consider the additional power requirements and signal integrity issues of supporting multiple loads on a high-speed bus. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz supports both uni-processor and multiprocessor implementations with support for up to four processors on each local processor bus, or system bus. The processor system bus I/O buffers operate using Assisted Gunning Transistor Logic, or AGTL+. The processor uses the S.E.C. cartridge package supported by the SC330 Connector (See Chapter 7 for the processor mechanical specifications.) The Pentium(R) III XeonTM processor includes an SMBus interface that allows access to several processor features, including two memory components (referred to as the Processor Information ROM and the Scratch EEPROM) and a thermal sensor on the processor substrate. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz system bus definition uses the SC330.1 interface. The SC330.1 interface is an electrical only enhancement to the SC330 (formerly Slot2) interface that allows supporting for a 4way Pentium(R) III XeonTM processor at 700 MHz and 900 MHz-based system running at 100 MHz system bus frequency. The SC330.1 specification adds the required flexibility to accommodate control and monitoring signals for an OCVR (On Cartridge Voltage Regulator). The OCVR provides the necessary high precision regulation used by Intel's latest silicon technology. This document provides information regarding the design of a system using the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz with the new SC330.1 bus specification. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz is designed to be compatible with previous SC330compliant baseboards given that an existing platform meets the signal integrity and timing requirements of Intel's latest silicon technology as specified in this document. For details on system compatibility requirements refer to the Pentium III Xeon Processor System Compatibility Guidelines. Certain versions of the processor are designed to be compatible with the existing VRM 8.3 Guidelines, allowing an easy transition for Flexible Mother Board designs. The 2.8V version of the processor (regardless of frequency and cache size) is designed for compatibility with the VRM 8.3 Guidelines. The 5V/12V version of the processor adds flexibility to operate at either 5 Volts or 12 Volts. The new flexible motherboard specification that incorporates the SC330.1 interface uses the same form factor and pin definition of the existing SC330 (formerly Slot 2) processors, but adds signals to control an OCVR and remote sensing capabilities. The SC330.1 enhancement is electrically and mechanically compatible with baseboards designed for the SC330 interface.
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TERMINOLOGY
2. TERMINOLOGY
In this document, a `#' symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a non-maskable interrupt has occurred. In the case of lines where the name does not imply an active state but describes part of a binary sequence (such as address or data), the `#' symbol implies that the signal is inverted. For example, D[3:0] = `HLHL' refers to a hex `A', and D [3:0] # = `LHLH' also refers to a hex `A' (H= High logic level, L= Low logic level). The term `system bus' refers to the interface between the processor, system core logic and other bus agents. The system bus is a multiprocessing interface to processors, memory and I/O. Cache coherency is maintained with other agents on the system bus through the MESI cache protocol as supported by the HIT# and HITM# bus signals. The term "processor" refers to the cartridge package that interfaces to a host system board through the SC330.1 interface specification. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz includes one processor core with integrated L2 cache, an OnCartridge Voltage Regulator (OCVR), system bus termination and various system management features. In addition, the processor includes a thermal plate for cooling solution attachment and a protective cover.
2.1 S.E.C. CARTRIDGE TERMINOLOGY The following terms are used in this document and are defined here for clarification:
* * Cover -- The processor casing on the opposite side of the thermal plate. Core pin -- The most external feature of the core package contained within the S.E.C. cartridge used to connect the core to an internal cartridge substrate trace. For measurement and specification purposes, the cartridge vias used to connect the core package to the cartridge substrate traces may be considered the core pins. Core pad -- A feature of a processor die contained within the core package used to connect the die to the core package. A core pad is defined in the processor signal integrity models and is only observable in simulation. Pentium(R) III XeonTM processor at 700 MHz and 900 MHz -- The SC330 processor including internal components, substrate, thermal plate and cover, with either 1MB or 2MB of on-die L2 cache, a 100 MHz system bus, and support for up to 4-way configurations. FMB (Flexible Motherboard Specification) -- A set of specifications to which a design is targeted to allow forward compatibility with existing and future processors. L1 cache -- Integrated static RAM used to maintain recently used information. Due to code locality, maintaining recently used information can significantly improve system performance in many applications. The L1 cache is integrated directly on the processor core. L2 cache -- The L2 cache is integrated directly on the processor core. OCVR -- On Cartridge Voltage Regulator, a new feature that provides the necessary regulated power to the processor core and Integrated L2 cache and is located on the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz substrate. 2.8V version -- refers to a Pentium(R) III XeonTM processor at 700 MHz and 900 MHz that can be powered with +2.8 volts applied to its VCC_CORE pins. 5V/12V version -- refers to a Pentium(R) III XeonTM processor at 700 MHz and 900 MHz that can be powered with either +5.0 or +12.0 volts applied to its VCC_CORE pins. HV_EN# -- pin added to the SC330.1 definition as a way of differentiating a 5V/12V version Pentium(R) III XeonTM processor at 700 MHz and 900 MHz from a 2.8V version. HV_EN# is tied to Vss (ground) on the 5V/12V version, and is high impedance (floating) on the 2.8V version. This is a reserved (no connect) pin on Pentium(R) III XeonTM processors. Processor substrate -- The structure on which components are mounted inside the S.E.C. cartridge (with or without components attached). Processor core -- The processor's execution engine. S.E.C. cartridge -- The processor packaging technology used for the Pentium(R) II XeonTM processor family. S.E.C. is short for "Single Edge Contact" cartridge. Streaming SIMD Extensions -- A new set of instructions supported by Intel(R) processors beginning with the Pentium(R) III XeonTM processor. Single Instruction Multiple Data (SIMD) extensions significantly accelerate performance of 3D graphics. Besides 3D graphics improvements, the extensions also include additional integer and cacheability instructions that improve other aspects of performance. Thermal plate -- The surface used to connect a heatsink or other thermal solution to the processor. 7
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TERMINOLOGY
Additional terms referred to in this and other related documentation: * SC330.1 -- An enhanced electrical and mechanical interface based on the SC330 (formerly Slot2) interface that defines additional signals and electrical requirements to support an OCVR (On Cartridge Voltage Regulator), a processor core and a System Bus frequency of 100 MHz for 4-way designs. Refer to Chapter 10 for details. Retention mechanism -- A mechanical component designed to hold the processor in a SC330 connector.
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2.2 State of Data
The data contained within this document is subject to change. It is the best information that Intel(R) is able to provide by the publication date of this document.
2.3 References
The reader of this specification should also be familiar with material and concepts presented in the following documents: * * * * * CPU-ID Instruction Application Note (Order Number 241618) Pentium(R) III XeonTM Processor at 700 MHz and 900 MHz Signal Integrity Models, IBIS Format (www.developer.intel.com) Intel(R) Pentium(R) III XeonTM Processor Specification Update (Order Number 244460) S330 Processor Enabling Technology Vendor List (www.developer.intel.com) Intel Architecture Software Developer's Manual (Order Number 243193) Volume I: Basic Architecture (Order Number 243190) Volume II: Instruction Set Reference (Order Number 243191) Volume III: System Programming Guide (Order Number 243192) * * * 330-Contact Slot Connector (SC330) Design Guidelines (http://developer.intel.com/design/pentiumii/xeon/designgd/index.htm) VRM 8.3 Specification (http://developer.intel.com/design/pentiumii/xeon/designgd/index.htm) Pentium(R) II XeonTM processor/Intel(R) 450NX PCIset AGTL+ Layout Guidelines (Order Number 243790)
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ELECTRICAL SPECIFICATIONS
3. ELECTRICAL SPECIFICATIONS 3.1 System Bus and VREF
The Pentium(R) III XeonTM processor signals use a variation of the Pentium(R) Pro processor GTL+ signaling technology. The Pentium(R) III XeonTM processor differs from the Pentium(R) II processor and Pentium(R) Pro processor in its output buffer implementation. The buffers that drive most of the system bus signals on the Pentium(R) III XeonTM processor are actively driven to VTT for one clock cycle after the low to high transition to improve rise-times and reduce noise. These signals should still be considered open-drain and require termination to a supply that provides the high signal level. Because this specification is different from the standard GTL+ specification, it is referred to as Assisted Gunning Transistor Logic (AGTL+) in this document. AGTL+ logic and GTL+ logic are compatible with each other and may both be used on the same system bus. For more information on the GTL+ specification, see the Pentium II Processor Developer's Manual (Order Number 243502). AGTL+ inputs use differential receivers that require a reference signal (VREF). The receivers use VREF to determine if a signal is a logical 0 or a logical 1. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz generates its own version of VREF. VREF must be generated on the baseboard for other devices on the AGTL+ system bus. Termination is used to pull the bus up to the high voltage level and to control signal integrity on the transmission line. The processor contains termination resistors, but additional termination on the baseboard may be necessary to maintain proper signal quality and timing for the processor and any additional system bus devices. Some of the electrical specifications assume a specific effective termination resistance. See test conditions described with each specification. Due to the existence of termination on each of up to 4 processors in a Pentium(R) III XeonTM processor at 700 MHz and 900 MHz, the AGTL+ bus is typically not a daisy chain topology as in previous P6 Family processor systems. Like the Pentium(R) II XeonTM processor, the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz timing specifications are defined to points internal to the processor cartridge. Analog signal simulation of the system bus is required when developing Pentium(R) III XeonTM processor at 700 MHz and 900 MHz-based systems to ensure proper operation over all conditions.
3.2 Power and Ground Pins
By implementing an On Cartridge Voltage Regulator (OCVR), the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz eliminates the need for high precision regulation from the flexible baseboard. A Pentium(R) III XeonTM processor at 700 MHz and 900 MHz platform could be implemented to supply operating voltages of the processor die and of the L2 cache die for compatibility with previous generations of the Pentium(R) III XeonTM processor. These voltages may differ from each other. Note that the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz does not require a dedicated L2 supply and that VID logic will assume L2 supply is not required. (Please refer to the VRM 8.3 specification for details). The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz FMB allows compatibility with previous Pentium(R) III XeonTM processors. In an FMB that supports Pentium(R) III XeonTM processor, there must be two groups of power inputs to support the voltage difference between the components in the package. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz will not use the voltage identification (VID) pins for L2 Cache (VID_L2), but a system that supports the previous generation of Pentium(R) III XeonTM processors must use those pins to supply the correct voltages to the processor L2 cache. In a FMB design, there are five pins defined on the package for core voltage identification (VID_CORE), and five pins defined on the package for L2 cache voltage identification (VID_L2). These pins specify the voltage required by the processor core and L2 cache respectively. A Pentium(R) III XeonTM processor at 700 MHz and 900 MHz relies on the VID identification pins for the VCC_CORE required voltage level ONLY and does not require a separate L2 voltage supply. For signal integrity improvement and clean power distribution within the S.E.C. package, the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz FMB has 65 VCC (power) and 55 VSS (ground) inputs (see section 7.3 for a complete edge finger signal listing). The 65 VCC pins are further divided to provide the different voltage levels to the components. VCC_CORE inputs for the processor core account for 35 of the VCC pins, while 8 VTT inputs (1.5V) are used to provide an AGTL+ termination voltage to the processor. The 20 VCC_L2 inputs are not connected on the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz). One Vcc_SMB pin is provided for use by the SMBus, and one Vcc_TAP. The Vcc_SMB, Vcc_TAP, Vcc_L2 (on previous versions of the Pentium(R) III XeonTM only), and Vcc_CORE must remain electrically separated from each other. Vcc_SMB must be connected to a 3.3V power supply (even if the SMBus features are not used) in order for the processor to function properly. On the baseboard, all VCC_CORE pins must be connected to a voltage plane. Similarly, all VSS pins must be connected to a system ground plane.
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ELECTRICAL SPECIFICATIONS
For a summary of the power and ground pins listed above, see Table 50 and Table 51 in section 7.3 of this document for signal listings by Pin Number and Pin Name.
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ELECTRICAL SPECIFICATIONS
3.3 Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or a reduced lifetime of the component. 3.3.1 VCC_CORE The power input should provide bulk capacitance with a low Effective Series Resistance (ESR) and the system designer must also control the interconnect resistance from the regulator (or VRM pins) to the SC330 connector. Simulation is required for first and second order characterization. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, is provided on the voltage regulation module (VRM) defined in the VRM 8.3 DC-DC Converter Design Guidelines. The input to VCC_CORE should be capable of delivering a recommended minimum dICCCORE/dt defined in Table 6 while maintaining the required tolerances defined in Table 5. 3.3.2 LEVEL 2 CACHE DECOUPLING The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz does not require the VccL2 pins for power, however for systems that are designed to support this processor as well as previous Pentium(R) II XeonTM and Pentium(R) III XeonTM processors, the regulator solutions need to implement and provide bulk capacitance with a low Effective Series Resistance (ESR) in order to meet the tolerance requirements for VCCL2 of previous processors. Use similar design practices as those recommended for VCC_CORE. 3.3.3 SYSTEM BUS AGTL+ DECOUPLING The processor contains high frequency decoupling capacitance on the cartridge substrate; the system baseboard must provide bulk decoupling for proper AGTL+ bus operation. High frequency decoupling may be necessary at the SC330 connector to further improve signal integrity if noise is introduced at the connector interface.
3.4 Clock Frequencies and System Bus Clock Ratios
The Pentium(R) III XeonTM processor uses a clock ratio design in which the bus clock is multiplied by a ratio to produce the processors internal ("core") clock. The Pentium(R) III XeonTM processor at 700 MHz begins sampling A20M#, IGNNE#, LINT[0], and LINT[1] on the inactive-to-active transition of RESET# to determine the core-frequency to bus-frequency relationship, and the PLL immediately begins to lock on to the input clock. However, the Pentium(R) III XeonTM processor at 900 MHz ignores the logic states presented to the core/bus ratio pins at the de-assertion of the RESET# signal, and will operate only with a 9:1 core/bus ratio. On the active-to-inactive transition of RESET#, the Pentium(R) III XeonTM processor at 700 MHz internally latches the inputs to allow the pins to be used for normal functionality. Effectively, these pins must meet a large setup time (1ms) to the active-to-inactive transition of RESET# (see RESET# and PWRGD relationship in Figure 41). These pins should then be held static for at least 2 bus clocks, but no longer than 20 bus clocks.
11
ELECTRICAL SPECIFICATIONS
Table 1 System Bus-to-Core Frequency Ratio Configuration1 Ratio of BCLK to Core Frequency 1/4 (Safe-LLLL) 1/7 2/182 1/4(Safe-HHHH) 100 MHz Target Frequency 700 MHz 900 MHz EBL PWRUP Reg[27, 25:22] 0 0011 0 1001 1 0000 0 1100 LINT[1] LINT[0] IGNNE# A20M#
L H X H
L L X H
L H X H
L L X H
NOTES: 1. The frequency multipliers supported are shown in Table 1; other combinations will not be validated nor supported by Intel. Also, each
2. multiplier is only valid for use on the product of the frequency indicated in Table 1. The Pentium(R) III XeonTM processor at 900 MHz with 2MB of L2 cache will ignore the logic states presented to the core/bus ratio pins (A20M#, IGNNE#, LINT0, and LINT1) at the de-assertion of the RESET# signal, and will operate only with a 9:1 core/bus ratio.
Clock multiplying within the processor is provided by the internal PLL, requiring a constant frequency BCLK input. The BCLK frequency ratio cannot be changed dynamically during normal operation or any low power modes. The BCLK frequency ratio for the Pentium(R) III XeonTM processor at 700 MHz can be changed when RESET# is active, assuming that all RESET# specifications are met. See Figure 1 for the timing relationship between the system bus multiplier signals, RESET#, and normal processor operation. Using CRESET# (CMOS Reset) and the timing shown in Figure 1, the circuit in Figure 2 can be used to share these configuration signals. The component used as the multiplexer must not have outputs that drive higher than 2.5V in order to meet the processor's 2.5V tolerant buffer specifications. As shown in Figure 2, the pull-up resistors between the multiplexer and the processor (1K) force a "safe" ratio into the processor in the event that the processor powers up before the multiplexer and/or core logic. This prevents the processor from ever seeing a ratio higher than the final ratio. If the multiplexer were powered by VCC2.5, a pull-down resistor could be used on CRESET# instead of the four pull-up resistors between the multiplexer and the processor. In this case, the multiplexer must be designed such that the compatibility inputs are truly ignored, as their state is unknown. In any case, the compatibility inputs to the multiplexer must meet the input specifications of the multiplexer. This may require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already compatible.
B LK C
R ET# ES
C ES R ET#
RP atio ins#
Final R atio
Final R atio
C patibility om
000917
Figure 1. Timing Diagram of Clock Ratio Signals
12
ELECTRICAL SPECIFICATIONS
2.5 V 1K 2.5 V
Mux
A20M# IGNNE# LINT1/NMI LINT0/INTR
1-4 Processors
Set Ratio:
CRESET#2
000809 Figure 2. Logical1 Schematic for Clock Ratio Pin Sharing NOTES: 1. Signal Integrity issues may require this circuit to be modified 2. Current Intel(R) 840 chipsets do not implement the CRESET# signal. 3.4.2 MIXING PROCESSORS OF DIFFERENT FREQUENCIES Mixing components of different internal clock frequencies is not supported and has not been validated by Intel. Operating system support for multi-processing with mixed frequency components should also be considered. Also, Intel(R) does not support or validate operation of processors with different cache sizes. Intel(R) only supports and validates multi-processor configurations where all processors operate with the same system bus and core frequencies and have the same L1 and L2 cache sizes. Since the Pentium(R) III XeonTM processor at 900 MHz with 2MB of L2 cache will operate only with a 9:1 core/bus ratio, this processor should only be used in systems containing identical processors. Intel(R) does not support or validate the mixing of Pentium(R) III XeonTM processors at 500 MHz and 550 MHz, Pentium(R) III XeonTM processors at 700 MHz and 900 MHz, Pentium(R) III XeonTM processors at 600 MHz to 1 GHz with 256KB L2 cache, and Pentium(R) II XeonTM processors on the same system bus, regardless of frequency or L2 cache sizes.
3.5 Voltage Identification
The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz FMB guidelines enable compatibility with systems originally designed for previous members of the Pentium(R) II XeonTM and Pentium(R) III XeonTM processor family. To provide power delivery flexibility, the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz is available in two different input voltage versions; one version operates at 2.8 Volts and the other at 5 Volts or 12 Volts. As in previous versions of Pentium(R) II XeonTM and Pentium(R) III XeonTM processors, the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz contains five voltage identification (VID) pins, which are used by the processor for OCVR voltage selection in combination with pin A3, which incorporates added functionality for power delivery schemes. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz incorporates a new pin (A3, HV_EN#) as a method to identify its ability to be powered by a 5V or 12V power supply. The HV_EN# signal is used as a way of differentiating a 5V/12V version processor cartridge from a 2.8V version. HV_EN# is tied to Vss (ground) on the 5V/12V version, and is high impedance (floating) on the 2.8V version. This is a reserved (no connect) pin on previous versions of the Pentium(R) III XeonTM processor. Since the L2 cache is integrated in the core, the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz does not require a VID code to specify cache voltage. Pentium(R) III XeonTM processor at 700 MHz and 900 MHz FMB designs could be implemented to provide the additional five voltage identification pins for L2 cache voltage selection if Pentium(R) II XeonTM processor and previous versions of Pentium(R) III XeonTM processor compatibility are desired. These pins may be used to support automatic selection of both power supply voltages as required by a specific cartridge. 13
ELECTRICAL SPECIFICATIONS
VID_CORE[4:0] controls the voltage supply to the processor core and VID_L2[4:0] controls the voltage supply to the L2 cache (in the case of the Pentium(R) II XeonTM processor and Pentium(R) III XeonTM processor at 500 MHz and 550 MHz). Both core and L2 use the same encoding as shown in Table 2. They are not driven signals, but are either an open circuit or a short circuit to VSS. The combination of opens and shorts defines the voltage required by the processor core (and L2 cache for the Pentium(R) II XeonTM processor and Pentium(R) III XeonTM processor at 500 MHz and 550 MHz), the VID_L2 lines on the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz are all left open (pulled high on the baseboard). The VID pins support variations in processor core voltages and L2 cache implementations among processors in the SC330 processor family. Table 2 shows the recommended range of values to support for both the processor core and the L2 cache. A `1' in this table refers to an open pin and `0' refers to a short to ground. The definition provided below is a superset of the definition previously defined for the Pentium(R) Pro processor (VID4 was not used by the Pentium(R) Pro processor) and is common to the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz (for VCC_CORE only), Pentium(R) II XeonTM and previous Pentium(R) III XeonTM processors. The power supply must supply the voltage that is requested or it must disable itself. To ensure the system is capable of supporting Pentium(R) III XeonTM processor at 700 MHz and 900 MHz, Pentium(R) II XeonTM processors and previous Pentium(R) III XeonTM processors, a system should support those voltages indicated with a bold x in Table 2.
14
ELECTRICAL SPECIFICATIONS
Table 2. FMB Core and L2 Voltage Identification Definition 1, 2 Processor pins VID4 VID3 VID2 00110b - 01111b 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES:
1. 2. 3. 4. 5. 6. 0 = processor pin connected to VSS, 1 = Open on processor; may be pulled up to TTL VIH on baseboard. See the VRM 8.3 DC-DC Converter Design Guidelines and/or the VRM 8.3 DC-DC Converter Design Guidelines. VRM output should be disabled for VCC_CORE values less than 1.80V. X = Required. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz does not require an L2 voltage supply. The VCC_L2 and L2 VID lines are "open" on the processor cartridge. Required for FMB compatibility, not necessary for the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz. This VID setting can be used in combination with HV_EN# pin (A3) for differentiating 2.8V version from 5V/12V version cartridges. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz incorporates an integrated L2 cache, which eliminates the requirement of a VRM to power the L2 cache. Legacy systems provide L2 VRMs for Pentium(R) II XeonTM processor or Pentium(R) III XeonTM processor at 500 MHz and 550 MHz support. In these legacy systems, the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz will pass VID[4:0] = 11111 to the L2 VRM, instructing it to disable its output voltage. Certain VRM designs will also de-assert their VRM_PWRGD output. VRM_PWRGD signals are generally used to derive a SYS_PWRGD signal. With VRM_PWRGD de-asserted, the SYS_PWRGD is likely to be de-asserted, and the system will not boot. OEMs should examine legacy system and VRM designs intended to support the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz to ensure that there is no adverse impact to SYS_PWRGD derivation. See Figures 41 and 42.
VID1
VID0
Vcc Reserved 2
Core3
L23,5
0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1.80 1.85 1.90 1.95 2.00 2.05 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.86 2.9 3.0 3.1 3.2 3.3 3.4 3.5 No core7
X X X X X X X
X X X X X X X X X X X X X
X
X
Core 4
7.
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power source of the regulator only if required by the regulator or external logic monitoring the VID[4:0] signals. The power source chosen to drive/pull up VIDs must be guaranteed to be stable whenever the supply to the voltage regulator is non-zero and the OCVR is enabled. An invalid VID while the output is coming up could lead to and incorrect voltage above VCC_CORE max. This will prevent the possibility of the processor supply going above VCC_CORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can be accomplished by using the input voltage to the converter for the VID line
15
ELECTRICAL SPECIFICATIONS
pull-ups. A resistor of greater than or equal to 10K may be used to connect the VID signals to the converter input. See the VRM 8.3 DC-DC Converter Design Guidelines for further information.
3.6
System Bus Unused Pins and Test Pins
Unless otherwise specified, All RESERVED_XXX pins must remain unconnected. Note that pins that are newly marked as RESERVED in this document may be tied to a power rail in existing baseboards. See Chapter 7 for a pin listing of the processor edge connector for the location of each reserved pin. NOTE: Pentium(R) III XeonTM processor at 700 MHz and 900 MHz pin A11 (RESERVED_A11) may be pulled-down to VSS for legacy compatibility. The TEST_2.5_A62 pin must be connected to 2.5 Volts via a pull-up resistor between 1K and 10K. For the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz 5V/12V version only, it is recommended that pins that were previously specified as TEST_VCC_CORE_XX (now specified TEST_2.5_XX), be connected to the VCC_2.5 supply through separate 10K resistors on the baseboard. However, there will be no damage to cartridges if existing platforms provide 2.8 Volts to the pull-up resistors. All TEST_VTT pins must be connected to the Vtt supply through individual 150 resistors. All TEST_VSS pins must be connected individually to the Vss supply through individual 1K resistors. PICCLK must always be driven with a valid clock input. and the PICD[1:0] lines must be pulled-up to 2.5V even when the APIC will not be used. A separate pull-up resistor to 2.5V (keep trace short) is required for each PICD line. For reliable operation, always connect unused inputs to an appropriate signal level. Unused AGTL+ inputs should be left as no connects; AGTL+ termination on the processor provides a high level. Unused active low CMOS inputs should be connected to 2.5V with a ~10K resistor. Unused active high CMOS inputs should be connected to ground (VSS). Unused outputs may be left unconnected. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For correct operation when using a logic analyzer interface, refer to Chapter 8 for design considerations.
3.7 System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. All system bus outputs should be treated as open drain and requires a high-level source provided externally by the termination or pull-up resistor. AGTL+ input signals have differential input buffers, which use 2/3 VTT as a reference level. AGTL+ output signals require termination to 1.5V. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. The AGTL+ buffers employ active negation for one clock cycle after assertion to improve rise times. The CMOS, Clock, APIC, and TAP inputs can each be driven from ground to 2.5V. The CMOS, APIC, and TAP outputs are open drain and should be pulled high to 2.5V. This ensures correct operation for the processor. Timings are specified into the load resistance as defined in the AC timing tables. See Chapter 8 for design considerations for debug equipment. The SMBus signals should be driven using standard 3.3V CMOS logic levels.
16
ELECTRICAL SPECIFICATIONS
Table 3. Processor pin Groups Group Name AGTL+ Input AGTL+ Output AGTL+ I/O Signals BPRI#, BR[3:1]#1, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# PRDY# A[35:03]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#1, D[63:00]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP# A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGD2, SMI#, SLP#2, STPCLK# FERR#, IERR#, THERMTRIP#2 BCLK PICCLK PICD[1:0] TCK, TDI, TMS, TRST# TDO SMBDAT, SMBCLK, SMBALERT#, WP VCC_CORE, Vcc_TAP, Vcc_SMB, VTT, VSS, RESERVED_XXX, SA[2:1], SELFSB[0:1], OCVR_EN, OCVR_OK, VIN_SENSE, CORE_AN_VSENSE, HV_EN#
CMOS Input CMOS Output System Bus Clock APIC Clock APIC I/O3 TAP Input3 TAP Output3 SMBus Interface Power/Other4
NOTES:
1. 2. 3. 4. The BR0# pin is the only BREQ# signal that is bi-directional. The internal BREQ# signals are mapped onto BR# pins based on a processor's agent ID. See Chapter 10 for more information. For information on these signals, see Chapter 10. These signals are specified for 2.5V operation. VTT is used for the AGTL+ termination. VSS is system ground. Vcc_TAP is the TAP supply. Vcc_SMB is the SM bus supply. Reserved pins must be left unconnected. Do not connect to each other.
3.7.2 ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK. All SMBus signals are synchronous to SMBCLK. TCK and SMBCLK can be asynchronous to all other clocks.
3.8 Access Port (TAP) Connection
Depending on the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor be first in the TAP chain and followed by any other components within the system. A voltage translation buffer should be used to drive the next device in the chain unless a component is used that is capable of accepting a 2.5V input. Similar considerations must be made for TCK, TMS, and TRST#. Multiple copies of each TAP signal may be required if multiple voltage levels are needed within a system. NOTE TDI is pulled up to VccTAP with ~150 on the processor cartridge. An open drain signal driving this pin must be able to deliver sufficient current to drive the signal low. Also, no resistor should exist in the system design on this pin, as it would be in parallel with this resistor.
17
ELECTRICAL SPECIFICATIONS
A Debug Port is described in Chapter 8. The Debug Port must be placed at the start and end of the TAP chain with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port. In an MP system, be cautious when including an empty SC330 connector in the scan chain. All connectors in the scan chain must have a processor or termination card installed to complete the chain between TDI and TDO or the system must support a method to bypass the empty connectors. SC330 terminator substrates should tie TDI directly to TDO. (See Chapter 8 for more details.)
3.9 Maximum Ratings
Functional operation at the absolute maximum and minimum is not implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. Table 4. Absolute Maximum Ratings Symbol TSTORAGE
VCC_CORE
Parameter Processor storage temperature Supply voltage with respect to VSS seen at the input of the OCVR Any processor SM supply voltage with respect to VSS Any processor TAP supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS CMOS & APIC buffer DC input voltage with respect to VSS SMBus buffer DC input voltage with respect to VSS Max PWR_EN[1:0] pin current
Min -40 -0.5
Max 85 Operating voltage + 1.0 Operating voltage + 1.0 3.3 + 1.65 3.3 7.0 100
Unit C V
Notes 3 1,2
VSMBus VCCTAP VinGTL VinCMOS VinSMBus IPWR_EN NOTES:
1. 2. 3.
-0.3 -0.3 -0.3 -0.3 -0.1
V V V V V mA 1
Operating voltage is the voltage to which the component is designed to operate. See Table 5.
VCC_CORE is the voltage input seen at the input of the OCVR device which may be 2.8V for one product version or 5V (or 12V) for
another product version. Please contact Intel(R) for storage requirements in excess of one year.
3.10
Processor DC Specifications
The voltage and current specifications provided in Table 5 and Table 6 are defined at the processor edge fingers. The processor signal DC specifications in Tables 7, 8 and 9 are defined at the processor core. Each signal trace between the processor edge finger and the processor core carries a small amount of current and has a finite resistance. The current produces a voltage drop between the processor edge finger and the core. Simulations should therefore be run versus these specifications to the processor core. See Chapter 1 for the processor edge finger signal definitions and Table 3 for the signal grouping. Most of the signals on the processor system bus are in the AGTL+ signal group. These signals are specified to be terminated to VTT. The DC specifications for these signals are listed in Table 7. To ease connection with other devices, the Clock, CMOS, APIC, SMBus and TAP signals are designed to interface at non-AGTL+ levels. The processor contains a voltage clamp device on the cartridge substrate between the core and edge fingers. This device "clamps" the 2.5V level CMOS, TAP, and APIC signals to 1.5V levels, which helps reduce overshoot levels at the processor core. All CMOS, TAP, Clock, and APIC signals interface with the voltage clamp, with the exception of BCLK, PICCLK and PWRGOOD. The DC specifications for these pins are listed in Table 8 and Table 9. 18
ELECTRICAL SPECIFICATIONS
NOTE Unless otherwise noted, each specification applies to all Pentium(R) III XeonTM processor at 700 MHz and 900 MHz. Where differences exist between processors, look for the table entries identified by "FMB" in order to design a Flexible Mother Board (FMB) capable of accepting the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz as well as the Pentium(R) II XeonTM processor and previous versions of the Pentium(R) III XeonTM processor. Specifications are only valid while meeting specifications for case temperature, clock frequency and input voltages. Care should be taken to read all notes associated with each parameter.
Table 5. Voltage Specifications 1 Symbol VCCCORE (2.8V version) Parameter VCC for 2.8V version processor Min Typ 2.8 Max Unit V Notes 2,3,4
VCCCORE
(2.8V version)
Tolerance, Static
Processor core voltage static tolerance at edge fingers
-0.085
0.085
V
6
VCCCORE (2.8V version) Processor core voltage Tolerance, Transient transient tolerance at edge fingers VCCCORE
(5V/12Vversion)
-0.130
0.130
V
6
VCC for 5V/12V version processor AGTL+ Bus Termination voltage SMBus supply voltage TAP supply voltage
4.75 11.4 1.365
5.0 12.0 1.50
5.25 12.6 1.635
V
4,6,7,8
VTT
V
1.5V 9%, 5
VCC_SMB VCC_TAP NOTES:
1. 2. 3. 4. 5.
3.135 2.375
3.3 2.50
3.465 2.625
V V
3.3V 5%, 9 2.5V 5%
6.
7. 8. 9.
Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. "FMB" is a suggested design guideline for flexible motherboard design. Failure to adhere to the FMB guidelines may impact system upgradeability. VCC_CORE supplies the processor core. FMB refers to the range of set points for all Pentium(R) III XeonTM processors. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 3.5 for more information. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz does not require a separate VCC_L2 voltage. Use the Typical Voltage specification along with the tolerance specifications to provide correct voltage regulation to the processor. Vtt is 1.5 +/- 9% (AC & DC) when the measurement is bandwidth limited to 20 MHz and measured at the SC 330 connector pin on the back (solder tail) side of the baseboard. This parameter is measured at the processor edge fingers. The SC330 connector is specified to have a pin self-inductance of 6.0 nH maximum, a pin-to-pin capacitance of 2 pF (maximum at 1 MHz), and an average contact resistance over the 6 VTT pins of 15 m maximum Z. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the processor edge fingers and to the processor core. Voltage must return to within the static voltage specification within 100 us after the transient event. The SC330 connector is specified to have a pin self-inductance of 6.0 nH maximum, a pin-to-pin capacitance of 2 pF (maximum at 1 MHz), and an average contact resistance of 15m maximum in order to function with the Intel(R) specified voltage regulator module (VRM 8.3). Contact Intel(R) for testing details of these parameters. Not 100% tested. Specified by design characterization. Pentium(R) III XeonTM processor at 700 MHz and 900 MHz 5V/12V version is to be operated by 5V or 12V, and is available for new designs that do not provide compatibility with previous versions of the Pentium(R) III XeonTM processor. 5V and 12V are specified at 5%. This parameter includes both static (noise & ripple) and transient tolerances at the edge fingers. Vcc_SMB must be connected to 3.3V power supply (even if the SMBus features are not used) in order for the processor to function properly.
19
ELECTRICAL SPECIFICATIONS
Table 6. Current Specifications 1,10 Symbol Icc_core @ 2.74V VCC_CORE Parameter 700 MHz 900 MHz Min Typ Max 13.9 17.0 Unit A Notes 2
Icc_core @ 4.75V VCC_CORE
700 MHz 900 MHz
8.4 10.3
A
2
Icc_core @ 11.4V VCC_CORE
700 MHz 900 MHz
3.5 4.3
A
2
Icc_core FMB
2.74V 4.75V 11.4V
19.0 11.0 5.0 0 0.3 1.2
A
1, 2, 10
IVTT ISGnt
Termination voltage supply current ICC Stop Grant for processor core 2.8V 5.0V 12.0V
A
4
-
-
10.0 5.6 2.3
A
3,5
ICCSLP
ICC Sleep for processor core 2.8V 5.0V 12.0V
-
-
10.0 5.6 2.3 10 5 100
A
3
DlccCORE/dt DlCCVTT/dt ICCTAP ICCSMBus NOTES:
1. 2. 3. 4.
Current slew rate Termination current slew rate ICC for TAP power supply ICC for SMBus power supply 3
A/s A/s mA mA
6,7 7
22.5
8
5. 6. 7.
Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. "FMB" is a suggested design guideline for flexible motherboard design. Vcc_core/Icc_core supplies the processor core, integrated L2 cache and OCVR. Max ICC measurements are measured at VCC minimum voltage (at VRM or system power supply output) under maximum signal loading conditions. This is the current required for a single processor. A similar current is drawn through the termination resistors of each load on the AGTL+ bus. VTT is decoupled on the SC330 cartridge such that negative current flow due to the active pull-up to VCC_CORE in the processor will not be seen at the processor fingers. The current specified is also for AutoHALT state. Maximum values are specified by design/characterization at nominal VCC and at the SC330 edge fingers. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
20
ELECTRICAL SPECIFICATIONS
8. 9. VCC_SMB must be connected to 3.3V power supply (even if the SMBus features are not used) in order for the processor to function properly. A disabled processor OCVR draws approximately 46 mA at 2.8V VCC_CORE from the motherboard VRM. If your system needs to maintain VRM regulation with a disabled processor (OCVR_EN inactive), the VRM output minimum load specification should be 46 mA or less. The FMB specification is applicable to 2.8V OCVR processors where a VRM is used as the power source.
10.
Table 7. AGTL+ Signal Groups, DC Specifications at the processor Core Symbol VIL VIH RONN RONP VOHTS IL NOTES:
1. 2. 3. 4. 5. 6. 7. 8. Processor core parameter correlated into a 25 resistor to a VTT of 1.5V. 0 Vin 1.5 +3%. 0 Vout 2 +5%. The processor core drives high for only one clock cycle. It then drives low or tri-states its outputs. VTT is specified in Table 5. Not 100% tested. Specified by design characterization. This RON specification corresponds to a VOL_MAX of 0.5V when taken into an effective 25 load to VTT of 1.5V. Vil/Vih are not guaranteed with respect to AC parameters. Specified under no load conditions at an I-V operating point of zero current and V=VTT conditions.
Parameter Input Low Voltage Input High Voltage nMOS On Resistance pMOS On Resistance Output High Voltage Tri-state Leakage current for the Inputs, Outputs and I/O
Min -0.150 1.15V
Max 0.9 VTT 12.5 85 VTT 15
Unit V V Ohm Ohm V A
Notes 4,7 1,4,7 5, 6 5, 8 1, 4 2, 3
Table 8. CMOS, TAP, Clock and APIC Signal Groups, DC Specifications at the processor edge fingers Symbol VIL Parameter Input Low Voltage Min -0.150 Max 0.7 Unit V Notes 6
VIH
(PICCLK & PWRGD only)
Input High Voltage
1.7 2.0
2.625 2.625
V V
2.5V + 5% maximum, 7 2.5V + 5% maximum, 4, 5
VOL
(APIC only)
Output Low Voltage
0.5 0.550
V V V A A pF
Parameter measured at 14mA Parameter measured at 20mA All outputs are open-drain to 2.5V + 5% 1 2 3
VOH ILI ILO Con NOTES:
1. 2. 3. 4. 5.
Output High Voltage Input Leakage Current Output Leakage Current I/O Pin Capacitance
2.625 100 100 25
0 VIN 2.625V. 0 VOUT 2.625V. Total capacitance of processor core and voltage clamp device. Does not include cartridge trace capacitance. Applies to all CMOS, TAP, Clock, and APIC signals except BCLK, PICCLK and PWRGOOD. This parameter applies to PICCLK. This parameter applies to PWRDG.
21
ELECTRICAL SPECIFICATIONS
6. 7. Maximum VIL at the processor core pin is specified as 2/3 VTT - 0.2V. Minimum VIH at the processor core pin is specified as 2/3 VTT + 0.2V.
Table 9. SMBus Signal Group, DC Specifications at the processor edge fingers Symbol VIL VIH VOL IOL IOL2 ILI ILO NOTES:
1. SMBALERT# is an open drain signal.
Parameter Input Low Voltage Input High Voltage Output Low Voltage Output Low Current Output Low Current Input Leakage Current Output Leakage Current
Min -0.3 0.7 x VccSMB
Max 0.3 x VccSMB 3.465 0.4 3
Unit V V V mA mA
Notes
3.3V + 5% maximum
Except SMBALERT# SMBALERT# 1
6 10 10
A A
Table 10. OCVR Control Signals, DC Specifications at the processor edge fingers Symbol VIL
OCVR_EN
Parameter Input Low Voltage
Min
Max 0.8
Unit V
Notes 2, 3
VIH
OCVR_EN
Input High Voltage
2.0
V
2, 3
VOL
OCVR_OK
Output Low Voltage
0.4
V
-1.5mA max
VOH
OCVR_OK
Output High Voltage
-
-
V
1
NOTES:
1. 2. 3. Driver configured as open drain connected to 3.3V (Vcc_SMB) through a 10K resistor. Vih_max (absolute) = 5.25 VDC when the OCVR is powered. If the OCVR on the processor is not operating, such as at initial system power up or if there is no power input to the processor, the input should be driven in such a way that no more than 20 mA can flow into the input (assuming it is connected to ground). This is equivalent to using a 270 or higher pull-up resistor tied to a typical 5V supply as the only source for driving the input high.
3.11
AGTL+ System Bus Specifications
Table 11 below lists parameters controlled within the processor to be taken into consideration. A reference voltage (VREF), derived on the processor cartridge from VTT, is used by the input buffers to determine the valid high and low levels. VREF should be set to the same level for other AGTL+ logic using a voltage divider on the baseboard. It is important that the baseboard impedance be held as tight as possible and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. See Layout Guidelines (section 2.4) for impedance recommendations.
22
ELECTRICAL SPECIFICATIONS
Table 11 Internal Parameters for the AGTL+ Bus Symbol RTT VREF Parameter Termination Resistor Bus Reference Voltage 0.733 VTT 100mV Min Typ 150 0.733 VTT 0.733 VTT + 100mV Max Units Ohm V Notes 1 2
NOTES:
1. 2. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz contains on-die termination resistors with +/-10% tolerance. VREF is generated on the processor substrate.
23
ELECTRICAL SPECIFICATIONS
3.12
System Bus AC Specifications
The system bus timings specified in this section are defined at the processor core pins unless otherwise noted. Timings are tested at the processor core during manufacturing. NOTE: Timing specifications T45-T49 are reserved for future use. All system bus AC specifications for the AGTL+ signal group are relative to the rising edge of the BCLK input. All AGTL+ timings are referenced to 2/3 VTT for both `0' and `1' logic levels unless otherwise specified.
24
ELECTRICAL SPECIFICATIONS
Table 12. System Bus AC Specifications (Clock) at the processor Core Pins 1, 2, 3 T# Parameter System Bus Frequency Min 90 Nom Max 100.2 Unit MHz Figure Notes 4
T1: T2: T3: T4: T5: T6: NOTES:
1. 2. 3. 4. 5. 6.
BCLK Period BCLK Period Stability BCLK High Time BCLK Low Time BCLK Rise Time BCLK Fall Time
10.0
11.11 150
nS pS nS nS
4
4, 5, 9 6, 7, 9
2.5 2.5 0.50 0.50 1.5 1.5
4, 12 4, 12 4, 12 4, 12
@>2.0V, 9 @<0.5V, 9 0.5V-2.0V 8, 9 2.0V-0.5V 8, 9
nS nS
7.
8. 9.
Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00V at the processor core pins. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1V at the processor core pins. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to core clock ratio is determined during initialization as described in 6.2. Table 1 shows the supported ratios for each processor. The BCLK period allows a +0.5 nS tolerance for clock driver variation. See the CK98WS Clock Synthesizer/Driver Specification for further information. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be measured on the rising edges of adjacent BCLKs crossing 1.25V at the processor core pin. The jitter present must be accounted for as a component of BCLK timing skew between devices. The clock driver's closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock driver. The -20 dB attenuation point, as measured into a 10 to 20 pF load, should be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a spectrum analyzer. See the CK98WS Clock Synthesizer/Driver Specification for further details. Not 100% tested. Specified by design characterization as a clock driver requirement. This frequency range is specified by the CK98WS Clock Synthesizer/Driver Specification, and is guaranteed by design only (not tested).
25
ELECTRICAL SPECIFICATIONS
Table 14. AGTL+ Signal Group, System Bus AC Specifications at the Core Pins1 RL = 25 ohms Terminated to 1.5V T# T7: T8: T9: T10: NOTES:
1. 2. 3. 4. 5. 6. 7. 8. These specifications are tested during manufacturing. Valid delay timings for these signals at the processor core assume a 25 termination to 1.5V. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#. RESET# can be asserted (active) asynchronously, but must be de-asserted synchronously to the bus clock. After the bus ratio on A20M#, IGNNE# and LINT[1:0] are stable, VCC_CORE, and BCLK are within specification, and PWRGD is asserted. See Figure 8, 40 & 41. Specification is for a minimum 0.40V swing from VREF - 200 mV to VREF + 200 mV. This assumes an edge rate of .3V/ns. Parameter specified with an AGTL+ signal crossing point of 1.0V with respect to BCLK voltage reference. Parameter specified with an AGTL+ signal crossing point of 1.1V with respect to BCLK voltage reference.
Parameter AGTL+ Output Valid Delay AGTL+ Input Setup Time AGTL+ Input Hold Time RESET# Pulse Width
Min -0.07 1.20 0.62 1.00
Max 2.65
Unit nS nS nS mS
Figure Figure 5 Figure 6 Figure 6 Figure 8
Notes 2, 8 3, 4, 6, 8 5 5
Table 15. CMOS, TAP, Clock and APIC Signal Groups, AC Specifications at the processor Core 1, 2 T# T14: Parameter CMOS Input Pulse Width, except PWRGD and LINT[1:0] Min 2 Max Unit BCLKs Figure Figure 5 Notes Active and Inactive states 3 4
T14B: LINT[1:0] Input Pulse Width T15: PWRGD Inactive Pulse Width
6 10
BCLKs BCLKs
Figure 5 Figure 8
NOTES:
1. 2. 3. These specifications are tested during manufacturing. Valid delay timings for these signals are specified into 100 to 2.5V. When driven inactive or after VCC_CORE, and BCLK become stable. PWRGD must remain below VIL_MAX from Table 8 until all the voltage planes meet the voltage tolerance specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 11 for at least 10 clock cycles. PWRGD must rise glitch-free and monotonically to 2.5V. If the BCLK signal meets its AC specification within 150ns of turning on then the PWRGD Inactive Pulse Width specification is waived and BCLK may start after PWRGD is asserted. PWRGD must still remain below VIL_MAX until all the voltage planes meet the voltage tolerance specifications.
4.
26
ELECTRICAL SPECIFICATIONS
Table 16. System Bus AC Specifications (Reset Conditions1) T# T16: Parameter Reset Configuration Signals (A[14:05]#, BR0#, FLUSH#, INIT#) Setup Time Reset Configuration Signals (A[14:05]#, BR0#, FLUSH#, INIT#) Hold Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time 2 Min 4 Max Unit BCLKs Figure Figure 8 Notes Before de-assertion of RESET After clock that deasserts RESET# Before de-assertion of RESET# After assertion of RESET# 1 After clock that deasserts RESET#
T17:
2
20
BCLKs
Figure 8
T18:
1
mS
Figure 8
T19:
5
BCLKs
Figure 8
T20:
20
BCLKs
Figure 8 Figure 9
NOTES:
1. For a Reset, the clock ratio defined by these signals must be a safe value (their final or lower multiplier) within this delay unless PWRGD is being driven inactive.
Table 17. System Bus AC Specifications (APIC Clock and APIC I/O) at the processor Core Pins 1 T# T21: Parameter PICCLK Frequency Min 2.0 Max 33.3 Unit MHz Figure Notes
T22: T23: T24: T25: T26: T27: T28:
PICCLK Period PICCLK High Time PICCLK Low Time PICCLK Rise Time PICCLK Fall Time PICD[1:0] Setup Time PICD[1:0] Hold Time
30.0 12.0 12.0 0.25 0.25 5.0 2.5 1.5 1.5
500.0
nS nS nS
Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 6 Figure 6 Figure 5 Figure 5 5 5 2 2 2,3,4 2,3,4
3.0 3.0
nS nS nS nS
T29A: PICD[1:0] Valid Delay (Rising Edge) T29B: PICD[1:0] Valid Delay (Falling Edge) NOTES:
1. 2. 3. 4. 5.
8.7 12.0
nS nS
These specifications are tested during manufacturing. Referenced to PICCLK rising edge. For open drain signals, valid delay is synonymous with float delay. Valid delay timings for these signals are specified into a 150 resistor to 2.5V. This data is specified at the processor core.
27
ELECTRICAL SPECIFICATIONS
Table 18. System Bus AC Specifications (TAP Connection) at the processor Core 1 T# T30: T31: T32: T33: T34: T35: T36: T37: T38: T39: T40: T41: T42: T43: T44: NOTES:
1. 2. 3. 4. 5. 6. 7. 8. Unless otherwise noted, these specifications are tested during manufacturing. Not 100% tested. Specified by design characterization. 1 nS can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz. Referenced to TCK rising edge. Referenced to TCK falling edge. Valid delay timing for this signal is specified to 2.5V. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO and TMS). These timings correspond to the response of these signals due to TAP operations. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
Parameter TCK Frequency TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Non-Test Outputs Valid Delay All Non-Test Inputs Setup Time All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time
Min
Max 16.667
Unit MHz nS nS nS
Figure
Notes
60.0 25.0 25.0 5.0 5.0 40.0 5.0 14.0 1.0 10.0 25.0 2.0 25.0 25.0 5.0 13.0
Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 10 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 @1.7V 2 @0.7V 2 (0.7V-1.7V) 2, 3 (1.7V-0.7V) 2, 3 (Asynchronous) 2 4 4 5, 6 2, 5, 6 5, 7, 8 2, 5, 7, 8 4, 7, 8 4, 7, 8
nS nS nS nS nS nS nS nS nS nS nS
28
ELECTRICAL SPECIFICATIONS
Table 19. SMBus Signal Group, AC Specifications at the Edge Fingers T# T50: T51: T52: T53: T54: T55: T56: T57: T58: T59: NOTES:
1. Minimum time allowed between request cycles.
Parameter SMBCLK Frequency SMBCLK Period SMBCLK High Time SMBCLK Low Time SMBCLK Rise Time SMBCLK Fall Time SMBus Output Valid Delay SMBus Input Setup Time SMBus Input Hold Time Bus Free Time
Min
Max 100
Unit KHz uS uS uS
Figure
Notes
10 4.0 4.7 1.0 0.3 1.0 250 0 4.7
Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 5 Figure 6 Figure 6 1
uS uS uS nS nS uS
Table 20. OCVR Control Signals, AC Specifications at the Edge Fingers Parameter Min Max Unit Notes OCVR_EN High Time OCVR_EN Rise Time OCVR_EN Fall Time OCVR_OK Rise Time OCVR_OK Fall Time NOTES:
1. OCVR_OK output with 5pf load and 10K external pull-up to 3.3V.
10.0 10.0 10.0 30.0 10.0
uS uS uS nS nS 1 1
Figure 3 through Figure 10 are to be used in conjunction with the DC specification and AC timings tables.
Tr 2.0 V Th
Clock
0.5 V Tf Tp Tr = T5, T25, T34 (Rise Time) Tf = T6, T26, T36 (Fall Time) Th = T3, T23, T32 (High Time) Tl = T4, T24, T33 (Low Time) Tp = T1, T22, T31 (BCLK, PICCLK, TCK, Period) Tl
1.25 V
P6CB761z
Figure 3. BCLK, PICCLK, TCK Generic Clock Waveform
29
ELECTRICAL SPECIFICATIONS
T r SCLK 2.46V 0.84V
Th 2.97V 0.84V T f T l
Tr = T54 Tf = T55 Th = T52 Tl = T53
SMBUSCLK
Figure 4. SMBCLK Clock Waveform
Clock Tx Signal V Valid Valid Tx
Tpw Tx V = T7, T29 (Valid Delay) Tpw = T14, T15 (Pulse Wdith) = 2/3 V TT for GTL+ signal group; 1V for CMOS, and APIC signal groups
Figure 5. Valid Delay Timings
Clock K
Vclk Ts Th
Signal
V Valid
Ts = T8, T27 (Setup Time) Th = T9, T28 (Hold Time) V = 2/3 VTT for the GTL+ signal group; 1V for the CMOS, and APIC signal groups Vclk = 1.25V for BCLK, and PICCLK
000763z
Figure 6. Setup and Hold Timings
30
ELECTRICAL SPECIFICATIONS
BCLK
Tu Tt
RESET#
Tv
Configuration (A20M#, IGNNE#, LINT[1:0]) Configuration (A[14:5]#, BR0#, FLUSH#, INIT#)
Ty Safe
Tz Valid Tw Valid
Tx
Tt = T9 (GTL+ Input Hold Time) Tu = T8 (GTL+ Input Setup Time) Tv = T10 (RESET# Pulse Width) Tw = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) Tx = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time) Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
P6CB 764
Figure 7. System Bus Reset and Configuration Timings
BCLK V CC CORE V TT V CC
2.5
PWRGOOD Ta RESET# Configuration (A20M#, IGNNE#, LINT[1:0]) T a = T15 (PWRGOOD Inactive Pulse Width) T b = T10 (RESET# Pulse Width) T c = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
000765b
Tb
Tc Valid Ratio
Figure 8. Power-On Reset and Configuration Timings
31
ELECTRICAL SPECIFICATIONS
TCK
1.25V Tv Tw
TDI, TMS Non-Test Input Signals
1.25V Tr Ts
Tx
TDO Non-Test Output Signals
Tu
Ty
Tz
Tr = T43 (All Non-Test Inputs Setup Time) Ts = T44 (All Non-Test Inputs Hold Time) Tu = T40 (TDO Float Delay) Tv = T37 (TDI, TMS Setup Time) Tw = T38 (TDI, TMS Hold Time) Tx = T39 (TDO Valid Delay) Ty = T41 (All Non-Test Outputs Valid Delay) Tz = T42 (All Non-Test Outputs Float Delay)
6C 66
Figure 9. Test Timings (Boundary Scan)
TRST#
1.25V Tq
Tq = T36 (TRST# Pulse Width)
P6CBFigure 10. Test Reset Timings
32
SIGNAL QUALITY
4. Signal Quality
Signals driven on the system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long-term reliability of the component. Specifications are provided for simulation at the processor core. Meeting the specifications at the processor core in Table 21 through Table 27 ensures that signal quality effects will not adversely affect processor operation.
4.1 Bus Clock Signal Quality Specifications
Table 21 describes the signal quality specifications at the processor core pad for the processor system bus clock (BCLK) signal. Figure 11 shows the signal quality waveform for the system bus clock at the processor core pads. Table 21. BCLK Signal Quality Specifications at the Processor Core Pads1 V# V1: V2: V3: V4: V5: NOTES:
1. 2. Unless otherwise noted, all specifications in this table apply to all processor frequencies. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value.
Parameter BCLK VIL BCLK VIH VIN Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback
Min -0.3 2.0 -0.7 2.0
Nom
Max 0.5 2.625
Unit V V V V
Figure 11 11 11 11 11
Notes
2.0
3.3
2 2
0.5
V
T3
V3
V4 V2
V1 V5 V3
T6
T4
T5
000806
Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the processor Core Pads
33
SIGNAL QUALITY 4.2 AGTL+ Signal Quality Specifications
Refer to the Pentium II Processor Developer's Manual (Order Number 243341) for the specification for AGTL+. 4.2.2 AGTL+ Signal Quality Specifications Figure 12A illustrates the AGTL+ signal quality specifications for the processor for use in verifying signal quality at the processor core pins. These receiver signal quality specifications do not include overdrive region, ringback threshold, edge rate, and nonmonotonicity values. The receiver signal may contain ringback and non-monotonicity as long as these events do not occur inside the Setup and Hold Time windows. The Setup Time window is the shaded region, which is bounded by minimum VIH, maximum VIL, T8, and the BCLK 1.25V reference crossing point. The Hold Time window is the region bounded by minimum VIH, maximum VIL, T9, and the BCLK 1.25V reference crossing point. Note that the receiving signal at the receiver pin may contain non-ideal signal quality events within the T8 time, as long as these events occur outside the VIH / VIL Setup and Hold Time window boundaries. The following conditions apply to the processor signal quality specifications: 1. 2. 3. 4. A rising edge signal must cross above minimum VIH prior to the Setup Time window. A falling edge signal must cross below maximum VIL prior to the Setup Time window. A rising edge signal in the next cycle must cross minimum VIL outside the Hold Time window. A falling edge signal in the next cycle must cross maximum VIH outside the Hold Time window. A rising edge flight time uses a VIH crossing point. A falling edge flight time uses a VIL crossing point. Refer to the Pentium III Xeon processor at 700 MHz and 900 MHz Signal Integrity Models for a complete definition of flight time. For purposes of receiver signal quality, a nominal value of VREF (as defined in Table 10) should be used for all conditions. Therefore, the signal quality specifications given here already include sources of noise that will vary VIL and VIH. (e.g., VTT tolerance, VREF noise, VREF resistor divider tolerance, etc...). This receiver specification does not comprehend maximum overshoot/undershoot limits. Refer to the Section 4.2.3 for these specifications. Intel(R) recommends signal ringback with as much margin as possible to the VIH/VIL levels and T8/T9 times to allow margin for other sources of system noise.
5. 6.
AGTL+ Falling Edge Signal
1.25 V BCLK VRef
VIH VIL BCLK
AGTL+ Rising Edge Signal
T8
T8: AGTL+ Input Setup Time T9: AGTL+ Input Hold Time
T9
000914a
Figure 12A. Low to High AGTL+ Receiver Ringback Tolerance
4.2.3
AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES
Overshoot guidelines based on magnitude and duration of an overshoot/undershoot pulse (illustrated in Figure 13) are given in Table 23 and Table 24. 34
SIGNAL QUALITY
Overshoot/Undershoot is the absolute value of the maximum voltage differential across the input buffer relative to the termination voltage (VTT). The overshoot/undershoot guideline limits transitions beyond VTT or VSS due to the fast signal edge rates. The processor can be damaged by repeated Overshoot/Undershoot events on 1.5 V or 2.5 V tolerant buffers if the potential is large enough (i.e., if the overshoot/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the Magnitude, the Pulse Duration, and the Activity Factor. The Overshoot/Undershoot specifications apply to the processor, regardless of whether the processor is driving or receiving the signal. 4.2.3.1 Overshoot/Undershoot Magnitude Overshoot magnitude describes the maximum potential difference between a signal and its reference voltage level, Vss. Undershoot Magnitude describes the maximum potential difference between a signal and VTT (undershoot). While overshoot can be measured relative to VSS using one probe (probe on signal and ground lead on VSS), Undershoot must be measured relative to VTT. This can be accomplished by simultaneously measuring the VTT plane while measuring the signal undershoot. The true waveform can then be calculated by the oscilloscope itself or by the following oscilloscope data file analysis: Converted Undershoot Waveform = VTT - Signal Note: This Converted Undershoot Waveform appears as a positive (overshoot) signal. Note: Overshoot (rising edge) and Undershoot (falling edge) conditions are separate and their impact must be determined independently. After the conversion, the Overshoot/Undershoot Specifications can be applied to the Converted Undershoot Waveform using the Overshoot/Undershoot Magnitude and Pulse Duration Specifications in Tables 23, 24 and 25. Overshoot/Undershoot Magnitude levels must also observe the Absolute Maximum Specifications. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed Pulse Durations. Provided that the magnitude of the Overshoot/Undershoot is within the Absolute Maximum Specifications, the impact of the Overshoot/Undershoot Magnitude may be determined based upon the Pulse Duration and Activity Factor. 4.2.3.2 Overshoot/Undershoot Pulse Duration Overshoot/Undershoot Pulse Duration describes the total time that an Overshoot/Undershoot event exceeds the Overshoot/Undershoot Reference Voltage (Vos_ref = 1.635V). This total time could encompass several oscillations above the Overshoot/Undershoot Reference Voltage. Thus, multiple Overshoot/Undershoot pulses within a single Overshoot/Undershoot event must be measured to determine the total Pulse Duration. Note: Oscillations below the Reference Voltage cannot be subtracted from the total Overshoot/Undershoot Pulse Duration. Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered together as one event. Using the worst-case Overshoot/Undershoot Magnitude, sum together the individual Pulse Durations to determine the total Overshoot/Undershoot Pulse Duration for that total event. 4.2.3.3 Overshoot/Undershoot Activity Factor Activity Factor (AF) describes the frequency of Overshoot/Undershoot occurrence relative to a Clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other clock, an AF = 1 indicates that the specific Overshoot or Undershoot waveform occurs EVERY OTHER clock cycle (e.g., 1-0-1-0... system bus switching pattern). Thus, an AF = 0.01 indicates that the specific Overshoot or Undershoot waveform occurs 1 time in every 200 CLK cycles. The specifications provided in Tables 23, 24 and 25 show the Maximum Pulse Duration allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each Table entry is independent of all others, meaning that the Pulse Duration reflects the existence of Overshoot/Undershoot Events of that Magnitude ONLY. A platform with an overshoot/undershoot that just meets the Pulse Duration for a specific Magnitude where the AF < 1, means that there can be NO other Overshoot/Undershoot events, even of lesser Magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). Note: Activity Factor for AGTL+ signals is referenced to BCLK frequency. Note: Activity Factor for CMOS signals is referenced to PICCLK frequency.
4.2.3.4 Determining if a System Meets the Overshoot/Undershoot Specifications 35
SIGNAL QUALITY
The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that will each have their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail. A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. * Insure no signal (CMOS or AGTL+) ever exceed the 1.635V. * If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables. This means that whenever the over/undershoot event occurs, it always over/undershoots to the same level. * If multiple overshoots and/or multiple undershoots occur, measure the worst-case pulse duration for each magnitude and compare the results against the AF = 1 specifications (note: multiple overshoot/undershoot events within one clock cycle must have their pulse durations summed together to determine the total pulse duration). If all of these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table where AF=1, then the system passes.
Table 24. AGTL+ Signal Overshoot/Undershoot Limits at the Processor Core 1, 2,3,4,5,6,7,8,9,10 Overshoot/Undershoot Magnitude Max Pulse Duration (nS)
AF = 0.01 2.3 2.25 2.2 NOTES: 20 20 20
AF = 0.1 2.53 4.93 9.1
AF = 1 0.25 0.49 0.91
36
SIGNAL QUALITY
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Unless otherwise noted, all guidelines in this table apply to all processor frequencies. Overshoot Magnitude and Undershoot Magnitude are absolute values and should never exceed 2.3V under any circumstances. Overshoot is measured relative to VSS. Undershoot is measured relative to VTT. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V. Ringback below VTT cannot be subtracted from Overshoots/Undershoots. Lesser Undershoot does not allocate longer or larger Overshoot. Lesser Overshoot does not allocate longer or larger Undershoot. OEM's are encouraged to follow Intel provided layout guidelines. All values specified by design characterization. Specifications apply regardless of whether the processor is driving or receiving.
Figure 13. Maximum Acceptable Overshoot/Undershoot Waveform1,2,3,4,5,6,7,8
NOTES:
1. 2. 3. 4. 5. 6. 7. 8. Overshoot Magnitude and Undershoot Magnitude are absolute values and should never exceed 2.3V under any circumstances. Overshoot is measured relative to VSS. Undershoot is measured relative to VTT. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V. Ringback below VTT cannot be subtracted from Overshoots/Undershoots. Lesser Undershoot does not allocate longer or larger Overshoot. Lesser Overshoot does not allocate longer or larger Undershoot. OEM's are encouraged to follow Intel provided layout guidelines. All values specified by design characterization.
4.3 Non-GTL+ Signal Quality Specifications
There are three signal quality parameters defined for non-AGTL+ signals: Overshoot/Undershoot, Ringback, and Settling Limit. All three signal quality parameters are shown in Figure 14 for the non-AGTL+ signal group at the processor core 37
SIGNAL QUALITY
pads. Overshoot/Undershoot shown in Figure 14 is for illustrative purposes only to help explain Ringback and Settling Limit. Refer to Figure 13 for an illustration of Overshoot/Undershoot specifications.
O vershoot S ettling Lim it
V=I H
V CC 2 .5
R ising-E dge R ingback V o ltag e S ettling Lim it
F alling-E dge R ingback
V LO
V
SS
T im e U ndershoot
RINGBACK
Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback
4.3.1 2.5V Signal Overshoot/Undershoot Guidelines The Overshoot/Undershoot guideline limits transitions beyond VCC or VSS due to fast signal edge rates. Refer to Figure 14 for an illustration of Overshoot/Undershoot specifications for non-AGTL+ signals. The processor may be damaged if Overshoot/Undershoot specifications are not met. The Overshoot/Undershoot specification is shown in Table 26.
Table 27. 2.5V Tolerant Signal Group Overshoot/Undershoot at the Processor Core Pins1,2,3,4,5,6,7,8,9 Overshoot/Undershoot Max Pulse Duration (nS) Magnitude AF = 0.01 AF = 0.1 AF = 1 2.3 2.25 2.2 2.15 2.1 2.05 2.0 NOTES: 60 60 60 60 60 60 60 7.6 14.8 27.2 50 60 60 60 0.76 1.48 2.7 5 9.1 16.4 30
38
SIGNAL QUALITY
1. 2. 3. 4. 5. 6. 7. 8. 9. Activity Factor based on period equal to 30 nS. Overshoot/Undershoot Magnitude = 2.3V is an Absolute value and should never be exceeded. Overshoot is measured relative to VSS. Undershoot is measured relative to VTT. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V. Ringback below VTT cannot be subtracted from Overshoots/Undershoots. Lesser Undershoot does not allocate longer or larger Overshoot. OEM's are encouraged to follow Intel provided layout guidelines. All values specified by design characterization.
4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications Unlike AGTL+ or CMOS signals, BCLK Specifications do not provide for any relaxation due to activity factor. System designers should ensure that their platforms meet the BCLK specifications even under worst-case conditions. Intel recommends that platforms meet the Absolute Maximum Specifications for Overshoot and Undershoot on BCLK. This ensures that the BCLK I/O buffer will meet specifications regardless of Overshoot or Undershoot Pulse Duration within a clock cycle with 50% duty cycle. For all processors, the maximum BCLK Overshoot level is 3.3V. The Absolute maximum Undershoot is -0.7V, where "maximum" is defined as the largest voltage potential below ground. However, the Absolute Maximum Specifications can be relaxed for BCLK Undershoot if the Pulse Duration is accounted for under worst-case conditions. Thus, a system with BCLK Undershoot below -0.7V must ensure that the worst case Pulse Duration is less than or equal to the allowed Max Pulse Duration for the Worst Case Undershoot Magnitude. See the tables in this section for complete details. Table 28. BCLK Undershoot Specifications1,2,3,4,5,6 Max Pulse Duration (nS) 2.13 2.80 3.73 5.00 5.00
Undershoot Magnitude -0.85 -0.8 -0.75 -0.7 -0.65 NOTES:
1. 2. 3. 4. 5. 6.
Undershoot is measured relative to VTT. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V. Ringback below VTT cannot be subtracted from Overshoots/Undershoots. Lesser Undershoot does not allocate longer or larger Overshoot. OEM's are encouraged to follow Intel provided layout guidelines. All values specified by design characterization.
4.3.3 Measuring BCLK Overshoot/Undershoot Overshoot on BCLK is measured relative to GND. By probing BCLK with an oscilloscope where the probe GND lead makes good contact to a processor GND pin, BCLK Overshoot can be accurately measured to determine if the system meets BCLK Overshoot Absolute Maximum Specifications. Undershoot on BCLK is also measured relative to GND, again by probing BCLK with an oscilloscope where the probe GND lead makes good contact to a processor GND pin. If the system does not meet the BCLK Undershoot Absolute Maximum Specifications, then the Worst Case Undershoot Magnitude must be measured and the Pulse Duration of the Undershoot must be accounted for. Pulse Duration measurements determine the total amount of time that the BCLK signal spends below GND. Measuring from the earliest Falling Edge GND crossover to the latest Rising Edge GND crossover provides the worst-case Undershoot Pulse Duration. When compared to the Specification Table, the Pulse Duration and the Worst Case Undershoot Magnitude then determines if the system meets the BCLK Overshoot/Undershoot Specifications. Note: the measured Pulse Duration must be less than or equal to the Specified Max Pulse Duration for a given Worst Case Undershoot Magnitude.
39
SIGNAL QUALITY
4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION The ringback specification is the voltage at a receiving pin that a signal rings back to after achieving its maximum absolute value. (See Figure 14 for an for an illustration of ringback.) Excessive ringback can cause false signal detection or extend the propagation delay. Violations of the signal ringback specification are not allowed for 2.5V tolerant signals. Table 30 shows signal ringback specifications for the 2.5V tolerant signals to be used for simulations at the processor core. Table 30. Signal Ringback Specifications for 2.5V Tolerant Signal Simulation at the processor Core Input Signal Group Non-AGTL+ Signals Non-AGTL+ Signals Transition 01 10 Maximum Ringback (with Input Diodes Present) 1.7 0.7 Unit V V Figure 14 14
4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. The amount allowed is 10% of the total signal swing (VHI - VLO) above and below its final value. A signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again. Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions.
40
PROCESSOR FEATURES
5. PROCESSOR FEATURES 5.1 Low Power States and Clock Control
The processor allows the use of Auto HALT, Stop-Grant, and Sleep states to reduce power consumption by stopping the clock to specific internal sections of the processor, depending on each particular state. There is no Deep Sleep state on the processor. Refer to the following sections on low power states for the processor. For the processor to fully realize the low current consumption of the Stop Grant, and Sleep states, an MSR bit must be set. For the MSR at 02AH (Hex), bit 26 must be set to a `1' (power on default is a `0') for the processor to stop all internal clocks during these modes. For more information, see the Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide (Order Number 243192). Due to not being able to recognize bus transactions during Sleep state, SMP systems are not allowed to have one or more processors in Sleep state and other processors in Normal or Stop Grant states simultaneously. 5.1.1 NORMAL STATE -- STATE 1
This is the normal operating state for the processor. 5.1.2 AUTO HALT POWER DOWN STATE -- STATE 2
Auto HALT is a low power state entered when the processor executes the HALT instruction. The processor will issue a normal HALT bus cycle on BE[7:0]# and REQ[4:0]# when entering this state. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. SMI# will cause the processor to execute the SMI handler. The return from the SMI handler can be to either Normal Mode or the Auto HALT Power Down state. See Chapter 11 in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide. FLUSH# will be serviced during Auto HALT state. The on-chip first level caches and external second level cache will be flushed and the processor will return to the Auto HALT state. A20M# will be serviced during Auto HALT state; the processor will mask physical address bit 20 (A20#) before any look-up in either the on-chip first level caches or external second level cache, and before a read/write transaction is driven on the bus. The system can generate a STPCLK# while the processor is in the Auto HALT Power Down state. The processor will generate a Stop Grant bus cycle when it enters the Stop Grant state from the HALT state. If the processor enters the Stop Grant state from the Auto HALT state, the STPCLK# signal must be de-asserted before any interrupts are serviced (see below). When the system de-asserts the STPCLK# interrupt signal, the processor will return execution to the HALT state. The processor will not generate a new HALT bus cycle when it re-enters the HALT state from the Stop Grant state.
41
PROCESSOR FEATURES
HA L T Instruction and HA L T Bus Cycle Generated 2. Auto H AL T Power Down State BCL K running. Snoops and interrupts allowed. INIT#, BINIT#, INTR, NM I, SM I#, RESET# 1. Nor mal State Normal execution.
ST P C
LK#
Snoop Event Occurs
Snoop Event Serviced
ST P C
A sse rted
LK#
D e-a ssert ed
STPCL K # A sserted
STPCL K # De-asserted
4. H AL T /Grant Snoop State BCL K running. Service snoops to caches.
Snoop Event Occurs Snoop Event Serviced
3. Stop Gr ant State BCL K running. Snoops and interrupts allowed.
SL P# A sserted
SL P# De-asserted
5. Sleep State BCL K running. No snoops or interrupts allowed.
P6CB757a P6CB757b
Figure 15. Stop Clock State Machine
5.1.3
STOP-GRANT STATE -- STATE 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted. The processor will issue a Stop-Grant Transaction Cycle. Exit latency from this mode is 10 BLCK periods after the STPCLK# signal is de-asserted. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from Stop-Grant state. FLUSH# will not be serviced during Stop Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK# signal. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop phase on the system bus. A transition to the Sleep state will occur with the assertion of the SLP# signal. While in the Stop Grant State, all other interrupts will be latched by the processor, and only serviced when the processor returns to the Normal State. 5.1.4 HALT/GRANT SNOOP STATE -- STATE 4
The processor will respond to snoop phase transactions (initiated by ADS#) on the system bus while in StopGrant state or in Auto HALT Power Down state. When a snoop transaction is presented upon the system bus, the processor will enter the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). After the snoop is serviced, the processor will return to the Stop-Grant state or Auto HALT Power Down state, as appropriate.
42
PROCESSOR FEATURES
5.1.5 SLEEP STATE -- STATE 5
The Sleep state is a very low power state in which the processor maintains its context, maintains the PLL, and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the StopGrant state (verified by the termination of the Stop-Grant Bus transaction cycle), the SLP# pin can be asserted, causing the processor to enter the Sleep state. The system must wait 100 BCLK cycles after the completion of the Stop-Grant Bus cycle before SLP# is asserted. For an MP system, all processors must complete the Stop Grant bus cycle before the subsequent 100 BCLK wait and assertion of SLP# can occur. The processor is in Sleep state 10 BCLKs after the assertion of the SLP# pin. The latency to exit the Sleep state is 10 BCLK cycles. The SLP# pin is not recognized in the Normal, or Auto HALT States. Snoop events that occur during a transition into or out of Sleep state will cause unpredictable behavior. Therefore, transactions should be blocked by system logic during these transitions. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals immediately after the assertion of the SLP# pin (one exception is RESET# which causes the processor to reinitialize itself). The system core logic must detect these events and de-assert the SLP# signal (and subsequently de-assert the STPCLK# signal for interrupts) for the processor to correctly interpret any bus transaction or signal transition. Once in the Sleep state, the SLP# pin can be de-asserted if another asynchronous event occurs. No transitions or assertions of signals are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal (with the exception of SLP# or RESET#) before the processor has returned to Stop Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop Grant State. If RESET# is driven active while the processor is in the Sleep State and normal operation is desired, the SLP# and STPCLK# should be de-asserted immediately after RESET# is asserted. 5.1.6 CLOCK CONTROL
During Auto HALT Power Down and Stop-Grant states, the processor will continue to process the snoop phase of a system bus cycle. The PICCLK signal should not be removed during the Auto HALT Power Down or Stop-Grant states. When the processor is in the Sleep state, it will not respond to interrupts or snoop transactions. PICCLK can be removed during the Sleep state. The processor will not enter any low power states until all internal queues for the second level cache are empty. When re-entering Normal state, the processor will resume processing external cache requests as soon as new requests are encountered.
5.2 System Management Bus (SMBus) Interface
The processor includes an SMBus interface that allows access to several processor features, including two memory components (referred to as the processor Information ROM and the Scratch EEPROM) and a thermal sensor on the processor substrate. These devices and their features are described below. The processor SMBus implementation uses the clock and data signals of the SMBus specification. It does not implement the SMBSUS# signals.
43
PROCESSOR FEATURES
R 10K 1/16W 5% OEM EEPROM Vcc A0 A1 R 10K 1/16W 5% A2 WP SC SD INTEL CPU EEPROM Vcc A0 A1 A2 WP SC SD
R 10K 1/16W 5%
A2D
A C Stby
R 10K 1/16W 5%
Core
ALERT Vcc# A0 A1 SC SD
R 10K 1/16W 5%
R 10K 1/16W 5%
R 10K 1/16W 5% R 10K 1/16W 5% R 10K 1/16W 5%
R 10K 1/16W 5%
SA1
SDA SCL
WP
SA0
SMB_V
1
SA2
SMBALERT
Figure 16. Logical Schematic of SMBus Circuitry
NOTES:
1. Actual implementation may vary. For use in general understanding of the architecture.
5.2.1
PROCESSOR INFORMATION ROM
The processor implements previously defined fields in the processor information ROM (PI-ROM) to allow visibility of core and On Cartridge Voltage Regulation (OCVR) voltage requirements. These features are present in other SC330 processors, but are used in a different way in the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz implements the OCVR device. This provides the flexibility to accommodate products with voltage input of 2.8V for one product version and 5V or 12V for a different product version. The 2.8V or 5V version is indicated in the PI-ROM "OCVR option 1 Input Voltage ID" field, while the 12V version is indicated in the "OCVR option 2 Input Voltage ID" PI-ROM field. The implementation of the PI-ROM in the processor allows software to view the desired voltage outputs of the power source (VRM or Power Supply) feeding the OCVR and of the OCVR itself. Software could compare those values to actual power source/OCVR outputs (using an A/D converter), and determine if the power source and OCVR are operating correctly. The implementation of the PI-ROM gives system designers a means of determining the proper OCVR Output Voltage requirements. Without these fields, the baseboard has no way of determining the OCVR Output Voltage requirements. The fields defined for the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz coincide as closely as possible with those for previous versions of the Pentium(R) III XeonTM processor. The meaningless (for Pentium(R) III XeonTM processor at 700 MHz and 900 MHz) "L2 Cache Voltage" field is replaced with a more useful "OCVR Output" field. The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz (SC330.1) has a pin defined (A56, "VIN_SENSE") that allows the baseboard to directly measure the actual OCVR input voltage, and pin (B83, "AN_CORE_VSENSE") that is an analog representation of the voltage at the OCVR output. This voltage can be compared with the desired voltage (indicated by the PIR field) to determine if the OCVR input / output voltage is varying from desired levels. 44
PROCESSOR FEATURES
Systems implementing analog sensing should read the PIROM first, then compare that value with the measured VIN_SENSE rather than assuming any specific value. The value of AN_CORE_VSENSE is implementation dependent and cannot be assumed to be any particular value. Systems may derive benefit by monitoring its stability, but should not make assumptions about its value. In Table 31, text in bold represents the new defined fields for the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz.
45
PROCESSOR FEATURES
Table 31. Processor Information ROM Format Offset/Section HEADER: 00h 01h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Dh PROCESSOR: 0Eh # of Bits 8 16 8 8 8 8 8 8 8 8 16 8 48 2 6 8 CORE: 16h 2 4 Function Data Format Revision EEPROM Size Processor Data Address Processor Core Data Address L2 Cache Data Address SEC Cartridge Data Address Part Number Data Address Thermal Reference Data Address Feature Data Address Other Data Address Reserved Checksum S-spec/QDF Number Sample/Production Reserved Checksum Processor Core Type Processor Core Family Notes Two 4-bit hex digits Size in bytes (MSB first) Byte pointer, 00h if not present Byte pointer, 00h if not present Byte pointer, 00h if not present Byte pointer, 00h if not present Byte pointer, 00h if not present Byte pointer, 00h if not present Byte pointer, 00h if not present Byte pointer, 00h if not present Reserved for future use 1 byte checksum Six 8-bit ASCII characters 00b = Sample only Reserved for future use 1 byte checksum From CPUID From CPUID (Family 6) 4 Processor Core Model From CPUID (Model 8) 4 2 16 Processor Core Stepping Reserved OCVR option 2 Input Voltage ID 16 OCVR option 2 Input Voltage Tolerance 8 16 16 Reserved Maximum Core Frequency OCVR option 1 Input Voltage ID 16 OCVR option 1 Input Voltage Tolerance 8 8 L2 CACHE: 25h 32 Reserved Checksum Reserved Voltage in mV (0=2.8V, 12000=5V/12V Edge finger tolerance in mV, +/(0=2.8V, 600=5V/12V) Reserved for future use 16-bit binary number (in MHz) Voltage in mV (2800=2.8V, 5000=5V/12V) Edge finger tolerance in mV, +/(130=2.8V, 250=5V/12V) Reserved for future use 1 byte checksum Reserved 46 From CPUID
PROCESSOR FEATURES
16 8 16 8 8 8 8 CARTRIDGE: 32h 32 2 6 8 PART NUMBERS: 38h 56 112 64 208 8 THERMAL REF.: 70h 8 16 8 FEATURES: 74h 32 24 1 1 1 1 1 1 1 1 4 4 8 OTHER: 7Eh NOTES:
1. OCVR Output Voltage not tested. Programmed per design target.
L2 Cache Size Reserved OCVR Output Voltage ID1 OCVR Output Voltage Tolerance, High OCVR Output Voltage Tolerance, Low Reserved Checksum Cartridge Revision Substrate Rev. Software ID Reserved Checksum Processor Part Number Processor BOM ID Processor Electronic Signature Reserved Checksum Thermal Reference Byte Reserved Checksum Processor Core Feature Flags Cartridge Feature Flags OCVR Present Serial Signature Electronic signature present Thermal Sense Device Present Thermal Reference Byte Present OEM EEPROM Present Core VID present L2 Cache VID present Number of Devices in TAP Chain Reserved Checksum Reserved
16-Bit binary number (in Kbytes)
Voltage in mV Core tolerance in mV, + Core tolerance in mV, Reserved for future use 1 byte checksum Four 8-bit ASCII characters 2-bit revision number Reserved for future use 1 byte checksum Seven 8-bit ASCII characters Fourteen 8-bit ASCII characters 64-bit identification number Reserved for future use 1 byte checksum See below Reserved for future use 1 byte checksum From CPUID
1= Present 0= Not Present 1= Present 0= Not Present 1= Present 0= Not Present 1= Present 0= Not Present 1= Present 0= Not Present 1= Present 0= Not Present 1= Present 0= Not Present Always Zero One 4-bit hex digit Reserved for future use 1 byte checksum Reserved for future use
16
47
PROCESSOR FEATURES
5.2.2
SCRATCH EEPROM
Also available on the SMBus is an EEPROM that may be used for other data at the system or processor vendor's discretion. This device has a pull-down on the WP control pin through a 10K resistor, as implemented on all previous Pentium(R) II XeonTM and Pentium(R) III XeonTM processors. This will allow the OEM EEPROM to be programmed in systems with no manipulation of this signal. Once programmed, the data in this OEM EEPROM can be write protected by asserting the active-high WP signal. The Scratch EEPROM is a 1024 bit part. 5.2.3 PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS
Four SMBus packet types are associated with the PIROM and Scratch EEPROM. Each of these packet transfers provides a device select address and read/write bit. The remaining parts of the transfer vary. Two of the packets, Send Byte and Receive Byte, transfer one additional byte after the device select. The other two packets, Write Byte and Read Byte, transfer two additional bytes after the device select. By using these four transfer types, complete access to the EEPROMs is possible. Send Byte loads an address into the memory device that is used for subsequent access. Send Byte does not change the contents of the EEPROM, just the address pointer within it. See Table 32 and explanation below. Receive Byte gets a byte of data from the memory device. It uses an address already loaded into the EEPROM device and returns the byte at that address. Repetitive use of Receive Byte to access an address range is possible. See Table 33 and explanation below. Write Byte transfers both an address and data byte into the memory device. It is a stand-alone write cycle. See Table 34. Read Byte transfers an address and gets a byte of data from the memory device. It is a stand alone read cycle. See Table 35. Both ROMs respond to SMBus packet types Send Byte, Receive Byte, and Read Byte. The Scratch EEPROM additionally responds to the packet type Write Byte. The EEPROM devices perform sequential read and page write modes that are not covered by the SMBus specification. However, by use of the four transfers described above, all transfer requirements to these devices can be achieved. NOTE: In Tables 32 - 35 below: S indicates a start condition (SDA falling while SCK high) P indicates a stop condition (SDA rising while SCK high) R/W* indicates a read/write not signal (1 = read, 0 = write) A* indicates an acknowledge* signal, (0 = acknowledge, 1 = not acknowledge). The selected SMBus slave device drives the shaded portions, while the SMBus master device under control of the host drives the clear portions. Table 32. Send Byte SMBus Packet S 1 Device Address 7 bits R/ W* 0 A* 0 Data 8 bits A* 0 P 1
Table 32 outlines the Send Byte packet, which provides an address to the device for later use. A device select field and a write bit, which are acknowledged by the device, follow the start condition. The following data byte is really an address, which is also acknowledged by the device. Finally the stop condition is signaled.
48
PROCESSOR FEATURES
Table 33. Receive Byte SMBus Packet S 1 Device Address 7 bits R/ W* 1 A* 0 Data 8 bits A* 1 P 1
Table 33 diagrams the Receive Byte packet that performs as a current address read. A device select address field and a read flag follow the start condition. The device decodes its address and drives acknowledge low. The data is returned by the device and the transfer is terminated by the controller providing negative acknowledge and a stop. Note that there is no data address provided, only the device address. The EEPROM internal address counter keeps track of the address accessed during the last read or write operation, incremented by one. Repeated current address reads will receive data from consecutive addresses. Address roll over will occur when the last byte of the device has been read. In this event it will roll over to the first byte of the device.
Table 34. Write Byte SMBus Packet S 1 Device Address 7 bits R/ W* 0 A* 0 Data Address 8 bits A* 0 Data 8 bits A* 0 P 1
Table 34 diagrams the Write Byte packet. This is effectively a Random Address Write function. The device select address, data offset address and write data are provided within the packet. A write flag follows the device address. Each of the three acknowledge pulses is driven by the EEPROM device. After the Write Byte packet is received the Scratch EEPROM device enters a timed writing mode during which it will not respond to further transfers. This timed writing mode will last approximately 10 milliseconds.
Table 35. Read Byte SMBus Packet S 1 Device Address 7 bits R/ W* 0 A* 0 Data Address 8 bits A * 0 S 1 Device Address 7 bits R/ W* 1 A* 0 Data 8 bits A* 1 P 1
Table 35 illustrates the Read Byte packet. This is effectively a Random Address Read function. This is actually two consecutive SMBus transfers, an address write followed by a current address read from the same device. In the address write portion, both device address and data address are acknowledged by the EEPROM. A second start condition then occurs, followed by a receive byte read such as diagrammed above. From the programming perspective, this may be treated as two separate transfers. 5.2.4 THERMAL SENSOR
The processor thermal sensor provides a means of acquiring thermal data from the processor with an exceptional degree of precision. The thermal sensor is composed of control logic, SMBus interface logic, a precision analog-to-digital converter, and a precision current source. The thermal sensor drives a small current through the p-n junction of a thermal diode located on the same silicon die as the processor core. The forward bias voltage generated across the thermal diode is sensed and the precision A/D converter derives a single byte of thermal reference data, or a "thermal byte reading." System management software running on the processor or on a microcontroller can acquire the data from the thermal sensor to thermally manage the system. Upper and lower thermal reference thresholds can be individually programmed for the thermal diode. Comparator circuits sample the register where the single byte of thermal data (thermal byte reading) is stored. These circuits compare the single byte result against programmable threshold bytes. The alert signal on the processor SMBus (SMBALERT#) will assert when either threshold is crossed. To increase the usefulness of the thermal diode and thermal sensor, the processor PIROM includes a Thermal Reference Byte determined by Intel through a specific manufacturing procedure. This procedure determines the Thermal Reference Byte and programs it into the PIROM. The Thermal Reference Byte is 49
PROCESSOR FEATURES
uniquely determined for each unit. The procedure causes each unit to dissipate its maximum power (which can vary from unit to unit) while at the same time maintaining the thermal plate at its maximum specified operating temperature. Correctly used, this feature permits an efficient thermal solution while preserving data integrity. The thermal byte reading can be used in conjunction with the Thermal Reference Byte in the processor Information ROM. Byte 9 of the processor Information ROM contains the address in the ROM of this byte, described in more detail in Section 5.2.5. The thermal byte reading from the thermal sensor can be compared to this Thermal Reference Byte, to provide an indication of the difference between the temperature of the processor core at the instant of the thermal byte reading and the temperature of the processor core under the steady state conditions of high power and maximum TPLATE specifications. The nominal precision of the least significant bit of a thermal byte is 1C. Reading the thermal sensor is explained in Section 5.2.6. The thermal sensor feature in the processor cannot be used to measure TPLATE. The TPLATE specification in Chapter 6 must be met regardless of the reading of the processor's thermal sensor in order to ensure adequate cooling for the entire processor. The thermal sensor feature is only available while VCC_CORE and VCC_SMB are at valid levels and the processor is not in a low-power state. 5.2.5 THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS
The thermal sensor responds to five of the SMBus packet types: write byte, read byte, send byte, receive byte, and ARA (Alert Response Address). The send byte packet is used for sending one-shot commands only. The receive byte packet accesses the register commanded by the last read byte packet. If a receive byte packet was preceded by a write byte or send byte packet more recently than a read byte packet, then the behavior is undefined. Tables 36 through 40 diagram the five packet types. In these figures, `S' represents the SMBus start bit, `P' represents a stop bit, `Ack' represents an acknowledge, and `///' represents a negative acknowledge. The thermal sensor transmits the shaded bits and the SMBus host controller transmits the bits that aren't shaded. Table 41 shows the encoding of the command byte. Table 36. Write Byte SMBus Packet S 1 Address 7 bits Write 1 Ack 1 Command 8 bits Ack 1 Data 8 bits Ack 1 P 1
Table 37. Read Byte SMBus Packet S 1 Address 7 bits Write 1 Ack 1 Command 8 bits Ack 1 S 1 Address 7 bits Read 1 Ack 1 Data 8 bits /// 1 P 1
Table 38. Send Byte SMBus Packet S 1 Address 7 bits Write 1 Ack 1 Command 8 bits Ack 1 P 1
Table 39. Receive Byte SMBus Packet S 1 Address 7 bits Read 1 Ack 1 Table 40. ARA SMBus Packet S 1 ARA 0001 100 Read 1 Ack 1 Address Device Address1 /// 1 P 1 Data 8 bits /// 1 P 1
NOTE:
50
PROCESSOR FEATURES
1. This is an 8-bit field. The device that sent the alert will respond to the ARA Packet with its address in the seven most significant bits. The least significant bit is undefined and may return as a `1' or `0'. See Section 5.2.7 for details on the Thermal Sensor Device addressing.
Table 41. Command Byte Bit Assignments Register RESERVED RRT RS RC RCR RESERVED RESERVED RRHL RRLL WC WCR RESERVED RESERVED WRHL WRLL OSHT RESERVED Command 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h - FFh Reset State N/A N/A N/A 0000 0000 0000 0010 0111 1111 1100 1001 0111 1111 1100 1001 N/A N/A N/A N/A N/A N/A N/A N/A Function Reserved for future use Read processor core thermal data Read status byte (flags, busy signal) Read configuration byte Read conversion rate byte Reserved for future use Reserved for future use Read processor core thermal diode THIGH limit Read processor core thermal diode TLOW limit Write configuration byte Write conversion rate byte Reserved for future use Reserved for future use Write processor core thermal diode THIGH limit Write processor core thermal diode TLOW limit One shot command (use send byte packet) Reserved for future use
All of the commands are for reading or writing registers in the thermal sensor except the one-shot command (OSHT). The one-shot command forces the immediate start of a new conversion cycle. If a conversion is in progress when the one-shot command is received, then the command is ignored. If the thermal sensor is in standby mode when the one-shot command is received, a conversion is performed and the sensor returns to standby mode. The one-shot command is not supported when the thermal sensor is in auto-convert mode. If the thermal sensor is in auto-convert mode and is between conversions, then the conversion rate timer resets, and the next automatic conversion takes place after a full delay elapses. The default command after reset is to a reserved value (00h). After reset, receive byte packets will return invalid data until another command is sent to the thermal sensor. This one-shot feature is currently susceptible to failure and should not be used (i.e. don't issue one-shot commands) when in auto convert mode. 5.2.6 5.2.6.1 THERMAL SENSOR REGISTERS Thermal Reference Registers
The processor core and thermal sensor internal thermal reference registers contain the thermal reference value of the thermal sensor and the processor core thermal diodes. This value ranges from +127 to -128 decimal and is expressed as a two's complement, eight-bit number. These registers are saturating, i.e. values above 127 are represented at 127 decimal, and values below -128 are represented as -128 decimal. 5.2.6.2 Thermal Limit Registers
The thermal sensor has two thermal limit registers; they define high and low limits for the processor core thermal diode. The encoding for these registers is the same as for the thermal reference registers. If the diode thermal value equals or exceeds one of its limits, then its alarm bit in the Status Register is triggered. 51
PROCESSOR FEATURES
5.2.6.3 Status Register
The status register shown in Table 42 indicates which (if any) thermal value thresholds have been exceeded. It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection. Once set, alarm bits stay set until a status register read clears them. A successful read to the status register will clear any alarm bits that may have been set, unless the alarm condition persists. Table 42. Thermal Sensor Status Register Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) Name BUSY RESERVED RESERVED RHIGH RLOW OPEN RESERVED RESERVED Function A one indicates that the device's analog to digital converter is busy converting. Reserved for future use Reserved for future use A one indicates that the processor core thermal diode high temperature alarm has activated. A one indicates that the processor core thermal diode low temperature alarm has activated. A one indicates an open fault in the connection to the processor core diode. Reserved for future use. Reserved for future use.
5.2.6.4
Configuration Register
The configuration register controls the operating mode (standby vs. auto-convert) of the thermal sensor. Table 43 shows the format of the configuration register. If the RUN/STOP bit is set (high) then the thermal sensor immediately stops converting and enters standby mode. The thermal sensor will still perform analog to digital conversions in standby mode when it receives a one-shot command. If the RUN/STOP bit is clear (low) then the thermal sensor enters auto-conversion mode. Table 43. Thermal Sensor Configuration Register Bit 7 (MSB) 6 Name RESERVED RUN/STOP Reset State 0 0 Function Reserved for future use. Standby mode control bit. If high, the device immediately stops converting, and enters standby mode. If low, the device converts in either one-shot mode or automatically updates on a timed basis.. Reserved for future use.
5-0
RESERVED
0
5.2.6.5
Conversion Rate Register
The contents of the conversion rate register determine the nominal rate at which analog to digital conversions happen when the thermal sensor is in auto-convert mode. Table 44 shows the mapping between conversion rate register values and the conversion rate. As indicated in Table 44, the conversion rate register is set to its default state of 02h (0.25 Hz nominally) when the thermal sensor is powered up. There is a 25% error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate. Table 44. Thermal Sensor Conversion Rate Register Register Contents 00h 01h 02h Conversion Rate (Hz) 0.0625 0.125 0.25 52
PROCESSOR FEATURES
03h 04h 05h 06h 07h 08h to FFh 0.5 1 2 4 8 Reserved for future use
5.2.7
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory components claim those of the form "1010XXYZb". The "XX" and "Y" bits are used to enable the devices on the cartridge at adjacent addresses. The Y bit is hard-wired on the cartridge to VSS (`0') for the Scratch EEPROM and pulled to VCC_SMB (`1') for the processor Information ROM. The "XX" bits are defined by the processor slot via the SA0 and SA1 pins on the SC330 connector. These address pins are pulled down (1K) to ensure that the memory components are in a known state in systems that do not support the SMBus, or only support a partial implementation. The "Z" bit is the read/write bit for the serial bus transaction. The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form "0011XXXZb", "1001XXXZb" or "0101XXXZb". The device's addressing, as implemented, uses SA2 and SA1 and includes a Hi-Z state for the SA2 address pin. Therefore the thermal sensor supports 6 unique resulting address ranges. To set the Hi-Z state for SA2, the pin must be left floating. The system should drive SA1 and SA0, and will be pulled low (if not driven) by the 10K pull-down resistor on the processor substrate. Attempting to drive either of these signals to a Hi-Z state would cause ambiguity in the memory device address decode, possibly resulting in the devices not responding, thus timing out or hanging the SMBus. As before, the "Z" bit is the read/write bit for the serial bus transaction. Note that addresses of the form "0000XXXXb" are reserved and should not be generated by an SMBus master. The thermal sensor latches the SA1 and SA2 signals at power up. System designers should ensure that these signals are at valid input levels before the thermal sensor powers up. This should be done by pulling the pins to VCCSMB or VSS via a 1K or smaller resistor. Additionally, SA2 may be left unconnected to achieve the tri-state or "Z" state. If the designer desires to drive the SA1 or SA2 pin with logic the designer must ensure that the pins are at valid input levels (see Table 9) before VCCSMB begins to ramp. The system designer must also ensure that their particular system implementation does not add excessive capacitance (>50 pF) to the address inputs. Excess capacitance at the address inputs may cause address recognition problems. Figure 16 shows a logical diagram of the pin connections. Table 45 and Table 46 describe the address pin connections and how they affect the addressing of the devices.
53
PROCESSOR FEATURES
Table 45. Thermal Sensor SMBus Addressing Address (Hex) Upper Address1 Slot Select SA1 3Xh 0011 0011 5Xh 0101 0101 9Xh 1001 1001 NOTES:
1. 2. Upper address bits are decoded in conjunction with the select pins. A tri-state or "Z" state on this pin is achieved by leaving this pin unconnected.
8-bit Address Word on Serial Bus SA2 0 0 Z2 Z2 1 1 b[7:0] 0011000Xb 0011010Xb 0101001Xb 0101011Xb 1001100Xb 1001110Xb
0 1 0 1 0 1
Note that system management software must be aware of the slot number-dependent changes in the address for the thermal sensor. Table 46. Memory Device SMBus Addressing Address (Hex) Upper Address1 Slot Select (SA1) Bit 3 0 0 0 0 1 1 1 1 (SA0) Bit 2 0 0 1 1 0 0 1 1 Memory Device Select Bit 1 0 1 0 1 0 1 0 1 Device Addressed R/W
Bits 7-4 A0h/A1h A2h/A3h A4h/A5h A6h/A7h A8h/A9h AAh/ABh ACh/ADh AEh/AFh 1010 1010 1010 1010 1010 1010 1010 1010
Bit 0 X X X X X X X X Scratch EEPROM 1 Processor Information ROM 1 Scratch EEPROM 2 Processor Information ROM 2 Scratch EEPROM 3 Processor Information ROM 3 Scratch EEPROM 4 Processor Information ROM 4
This addressing scheme is targeted for up to 4-way MP systems. More processors can be supported by using a multiplexed (or separate) SMBus implementation.
54
THERMAL SPECIFICATIONS
6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS
The processor contains a thermal plate for heatsink attachment. The thermal plate interface is intended to provide for multiple types of thermal solutions. This chapter will provide the necessary data for a thermal solution to be developed. See Figure 17 for thermal plate location.
Figure 17. Thermal Plate View
6.1 Thermal Specifications
This section provides power dissipation specifications for each version of the processor. The thermal plate flatness is also specified for the S.E.C. cartridge. 6.1.1 POWER DISSIPATION
Table 47 and 48 provide the thermal design power dissipation for the processor. While the processor core dissipates the majority of the thermal power, the system designer should also be aware of the thermal power dissipated by the OCVR. Systems should design for the highest possible thermal power, even if a processor with lower frequency is planned. The thermal plate is the attach location for all thermal solutions. The maximum temperature for the entire thermal plate surface is shown in Table 47 and 48. The processor power is dissipated through the thermal plate and other paths. The power dissipation is a combination of power from the OCVR, the processor core (with integrated L2 cache), and the AGTL+ bus termination resistors. The overall system thermal design must comprehend the Max Thermal power. The combined power from the processor core, the second level cache, and the OCVR that dissipates through the thermal plate is the Max Thermal power. The heatsink should be designed to dissipate the Max Thermal power. The thermal sensor feature of the processor cannot be used to measure TPLATE. The TPLATE specification must be met regardless of the reading of the processor's thermal sensor in order to ensure adequate cooling for the entire processor. 55
THERMAL SPECIFICATIONS
Table 47 Power Estimates 1 Frequency Core Power2 (W) 2.8V OCVR Power (W) 5V/12V OCVR Power (W) 2.8V Cartridge Power 3 (W) 5V/12V Cartridge Power 3 (W) 2.8V Thermal Power 4,8 (W) 5V/12V Thermal Power 4,8 (W) AGTL+ Power5 Min Tplate C Max Tplate C
700/100 900/100 FMB6
NOTES:
1. 2. 3. 4.
25.9 31.8
6.1 7.5
7.3 9.0
32.0 39.3
33.2 40.8
28.9 35.5 50
29.6 36.3 50
2 2
0 0 0
65 65 65
5. 6. 7.
8.
These values are specified at nominal VCC_CORE for the processor core with integrated L2 cache. Core power indicates the combined worst-case power that can be dissipated by the processor & L2 cache. This value will be determined after the product has been characterized. Cartridge power indicates the worst-case power that can be dissipated by the processor, L2 cache and the OCVR. It is not possible for the AGTL+ bus, and the processor core to all be at full power simultaneously. Thermal power (which OEM's should use for their thermal designs) indicates the worst-case power that can be dissipated by the processor, L2 cache and 50% of the OCVR (since the OCVR does not contact the Thermal Plate). De-rating the thermal design power may result in exceeding the Tplate maximum temperature specification, which may result in immediate system failure or degradation of the processor's functional lifetime. AGTL+ power is the worst-case power dissipated in the termination resistors for the AGTL+ bus. "FMB" is a suggested design guideline for a flexible motherboard design. A disabled processor OCVR draws approximately 46 mA at 2.8V VCC_CORE from the motherboard VRM. If your system needs to maintain VRM regulation with a disabled processor (OCVR_EN inactive), the VRM output minimum load specification should be 46 mA or less. The Thermal Power specifications have been recently redefined. These values are based on device characterization and do not reflect any silicon design changes to lower processor power consumption. Absolute power consumption has not changed; however, the maximum thermal power specifications are being updated to reflect actual silicon performance. The Thermal Power values represent the thermal design point required to cool the processor in the platform environment.
56
THERMAL SPECIFICATIONS
6.1.2
PLATE FLATNESS SPECIFICATION
The thermal plate flatness for the processor is specified to 0.010" across the entire thermal plate surface, with no more than a 0.003" step anywhere on the surface of the plate, as shown in Figure 18.
Figure 18. Plate Flatness Reference
6.2 Processor Thermal Analysis
6.2.1 THERMAL SOLUTION PERFORMANCE
Processor cooling solutions should attach to the thermal plate. The processor cover is not designed for thermal solution attachment. The complete thermal solution must adequately control the thermal plate below the maximum and above the minimum specified in Table 47 and 48. The performance of any thermal solution is defined as the thermal resistance between the thermal plate and the ambient air around the processor ( thermal plate to ambient). The lower the thermal resistance between the thermal plate and the ambient air, the more efficient the thermal solution is. The required thermal plate to ambient is dependent upon the maximum allowed thermal plate temperature (TPLATE), the local ambient temperature (TLA) and the thermal plate power (PPLATE). thermal plate to ambient = (TPLATE - TLA) / PPLATE The maximum TPLATE and the thermal plate power are listed in Table 47 and 48. TLA is a function of the system design. Table 49 provides the example of a resultant thermal solution performance for the processor at different ambient air temperatures around the processor.
Table 49. Example Thermal Solution Performance Thermal Solution Performance FMB (50 Watts) thermal plate to ambient (C/watt) 0.60 0.50 0.40 35C Local Ambient Temperature (TLA) 40C 45C
Theta thermal plate to ambient value is made up of two primary components: the thermal resistance between the thermal plate and heatsink (theta thermal plate to heatsink) and the thermal resistance between the heatsink and ambient air around the processor (theta heatsink to air). A critical, but controllable factor to decrease the resultant value of theta thermal plate to heatsink is management of the thermal interface between the thermal plate and heatsink. The other controllable factor (theta heatsink to air) is determined by 57
THERMAL SPECIFICATIONS
the design of the heatsink and airflow around the heatsink. General Information on thermal interfaces and heatsink design constraints can be found in AP-586, Pentium II Processor Thermal Design Guidelines (Order Number 243331). 6.2.2 THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE
Figure 19 shows suggested interface agent dispensing areas when using either Intel suggested interface agent. System issues in meeting the TPLATE requirements will determine actual user area and interface agent selections.
Figure 19. Interface Agent Dispensing Areas and Thermal Plate Temperature Measurement Points
NOTES:
6. Interface agent suggestions: ShinEtsu* G749 or Thermoset* TC330; Dispense volume adequate to ensure required minimum area of coverage when cooling solution is attached. Areas A and B are suggested for processor core and OCVR products. Recommended cooling solution mating surface flatness is no greater than 0.007" or flatter. Temperature of the entire thermal plate surface not to exceed 65C. Use any combination of interface agent, cooling solution, flatness condition, etc., to ensure this condition is met. Thermocouple measurement locations are the expected high temperature locations without external heat source influence. Ensure that external heat sources do not cause a violation of TPLATE requirements
7.
6.2.3 6.2.3.1
MEASUREMENTS FOR THERMAL SPECIFICATIONS Plate Temperature Measurement
58
THERMAL SPECIFICATIONS
To ensure functional and reliable processor operation, the processor's thermal plate temperature (TPLATE) must be maintained at or below the maximum TPLATE and at or above the minimum TPLATE specified in Table 47 and 48. Power from the processor core is transferred to the thermal plate at 2 locations. Figure 20 and 21 shows the locations for TPLATE measurement directly above these transfer locations. Thermocouples are used to measure TPLATE and special care is required to ensure an accurate temperature measurement. Before taking any temperature measurements, the thermocouples must be calibrated. When measuring the temperature of a surface, errors can be introduced in the measurement if not handled properly. Such measurement errors can be due to a poor thermal contact between the thermocouple junction and the measured surface, conduction through thermocouple leads, heat loss by radiation and convection, or by contact between the thermocouple cement and the heatsink base. To minimize these errors, the following approach is recommended: * * * Use 36 gauge or finer diameter K, T, or J type thermocouples. Intel's laboratory testing was done using a thermocouple made by Omega* (part number: 5TC-TTK-36-36). Attach each thermocouple bead or junction to the top surface of the thermal plate at the locations specified in Figure 19 using high thermal conductivity cements. A thermocouple should be attached at a 0 angle if no heatsink is attached to the thermal plate. If a heatsink is attached to the thermal plate but the heatsink does not cover the location specified for TPLATE measurement, the thermocouple should be attached at a 0 angle (refer to Figure 20). The thermocouple should be attached at a 90 angle if a heatsink is attached to the thermal plate and the heatsink covers the location specified for TPLATE measurement (refer to Figure 21). The hole size through the heatsink base to route the thermocouple wires out should be smaller than 0.150" in diameter. Make sure there is no contact between the thermocouple cement and heatsink base. This contact will affect the thermocouple reading.
* *
*
000899
Figure 20. Technique for Measuring TPLATE with 0 Angle Attachment
000900
Figure 21. Technique for Measuring TPLATE with 90 Angle Attachment
59
MECHANICAL SPECIFICATIONS
7. MECHANICAL SPECIFICATIONS
The processor use S.E.C. cartridge package technology. The S.E.C. cartridge contains the processor core, OCVR and other components. The S.E.C. cartridge package connects to the baseboard through an edge connector. Mechanical specifications for the processor are given in this section. See Section 1.1.1 for a complete terminology listing. Figure 22 shows the thermal plate side view and the cover side view of the processor. Figure 23 shows the S.E.C. cartridge cooling solution attachment feature details on the thermal plate and depict package form factor dimensions and retention enabling features of the S.E.C. cartridge. The processor edge connector defined in this document is referred to as "SC330.1". This connector definition is mechanically the same as the existing SC 300 (formerly Slot 2). See the SC330 connector specifications for further details on the edge connector. Table 50 and Table 51 provide the edge finger and SC330.1 connector signal definitions for processor. The signal locations on the SC330 edge connector are to be used for signal routing, simulation and component placement on the baseboard.
me001.wmf
Figure 22. Isometric View of S.E.C. Cartridge
NOTES: Use of retention holes and retention indents are optional. 11. For SC330 connector specifications, see the SC330 Connector Specification. 12. All dimensions in inches for figures 23 thru 28.
60
MECHANICAL SPECIFICATIONS
Figure 23. S.E.C. Cartridge Cooling Solution Attach Details (Notes follow)
61
MECHANICAL SPECIFICATIONS
Figure 24. S.E.C. Cartridge Retention Enabling Details (Notes follow)
62
MECHANICAL SPECIFICATIONS
Figure 25. SEC Cartridge Retention Enabling Details
Maximum protrusions of the mechanical heatsink attach media into cartridge during assembly or in an installed condition not to exceed 0.160" from external face of thermal plate. 2. Specified cover retention indent dimension is at the external end of the indent. Indent walls have 1.0degree draft, with the wider section on the external end. 3. Clip extension on internal surface of retention slots should be as little as possible and not to exceed 0.040". 12. Tapped holes for cooling solution attach. Max torque recommendation for a screw in tapped hole is 81 inch-lb. 63 1.
MECHANICAL SPECIFICATIONS
7.1 Weight
The maximum weight of a processor and thermal solution is approximately 500 grams.
7.2 Cartridge to Connector Mating Details
The staggered edge connector layout makes the processor susceptible to damage from hot socketing (inserting the cartridge while power is applied to the connector). Extra care should be taken to ensure hot socketing does not occur. The electrical and mechanical integrity of the processor edge fingers are specified for up to 50 insertion/extraction cycles.
Figure 26. Side View of Connector Mating Details
NOTES: 4. Dimensional variation when cartridge is fully installed and the substrate is bottomed in the connector. Actual system installed height and tolerance is subject to the user's manufacturing tolerance of SC330 connector to the baseboard. 5. Retention devices for this cartridge must accommodate this cartridge "Float" relative to connector, without preload to the edge contacts in "X" and "Y" axes. (See figure 22 for axis orientation) 10. Fully installed dimensions must be maintained by the user's retention device. Cartridge backout from fully installed position may not exceed 0.020.
Figure 27. Top View of Cartridge Insertion Pressure Points
64
MECHANICAL SPECIFICATIONS
Figure 28. Front View of Connector Mating Details
NOTES: Retention devices for this cartridge must accommodate this cartridge "Float" relative to connector, without preload to the edge contacts in "X" and "Y" axes.
65
MECHANICAL SPECIFICATIONS
7.3 Substrate Edge Finger Signal Listing
Table 50 is the processor substrate edge finger listing in order by pin number. Table 51 is the processor substrate edge connector listing in order by pin name. These tables reflect the new SC330.1 pin definition, new or changed pins definitions are shown in bold.
Table 50. Signal Listing in Order by Pin Number Pin No. A1 A2 A3 Pin Name RESERVED_A1 VCC_TAP HV_EN# Signal Buffer Type DO NOT CONNECT TAP Supply OPEN (2.8V OCVR) or SHORT TO Vss (5V/12V OCVR) Ground AGTL+ VTT Supply AGTL+ VTT Supply CMOS Output Ground CMOS Input Ground DO NOT CONNECT (new designs)/ or pulldown (legacy). CMOS Output Ground CMOS Input CMOS Output Ground CMOS Input TAP Input Ground TAP Output CMOS Input Ground Pull up to 2.5V CMOS Output Ground CMOS INPUT CMOS Input Ground CMOS I/O CMOS Input Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Pin No. B1 B2 B3 Pin Name PWR_EN[1] VCC_CORE OCVR_OK Signal Buffer Type Short to PWR_EN[0] Cartridge Vcc Open Drain Output
A4 A5 A6 A7 A8 A9 A10 A11
VSS VTT VTT SELFSB1 VSS SELFSB0 VSS RESERVED_A11
B4 B5 B6 B7 B8 B9 B10 B11
TEST_VSS_B4 VCC_CORE VTT VTT VCC_CORE RESERVED_B9 FLUSH# VCC_CORE
Pull down to VSS Cartridge Vcc AGTL+ VTT Supply AGTL+ VTT Supply Cartridge Vcc DO NOT CONNECT CMOS Input Cartridge Vcc
A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39
IERR# VSS A20M# FERR# VSS IGNNE# TDI VSS TDO PWRGD VSS TEST_2.5_A23 THERMTRIP# VSS OCVR_EN LINT[0] VSS PICD[0] PREQ# VSS BP#[3] BPM#[0] VSS BINIT# DEP#[0] VSS DEP#[1] DEP#[3]
B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39
SMI# INIT# VCC_CORE STPCLK# TCK VCC_CORE SLP# TMS VCC_CORE TRST# RESERVED_B22 VCC_CORE RESERVED_B24 RESERVED_B25 VCC_CORE TEST_2.5_B27 LINT[1] VCC_CORE PICCLK PICD[1] VCC_CORE BP#[2] RESERVED_B34 VCC_CORE PRDY# BPM#[1] VCC_CORE DEP#[2]
CMOS Input CMOS Input Cartridge Vcc CMOS Input TAP Clock Cartridge Vcc CMOS Input TAP Input Cartridge Vcc TAP Input DO NOT CONNECT Cartridge Vcc DO NOT CONNECT DO NOT CONNECT Cartridge Vcc Pull up to 2.5V CMOS Input Cartridge Vcc APIC Clock Input CMOS I/O Cartridge Vcc AGTL+ I/O DO NOT CONNECT Cartridge Vcc AGTL+ Output AGTL+ I/O Cartridge Vcc AGTL+ I/O 66
MECHANICAL SPECIFICATIONS
Table 50. Signal Listing in Order by Pin Number Pin No. A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 Pin Name VSS DEP#[5] DEP#[6] VSS D#[61] D#[55] VSS D#[60] D#[53] VSS D#[57] D#[46] VSS D#[49] D#[51] VSS VIN_SENSE VSS D#[42] D#[45] VSS D#[39] TEST_2.5_A62 VSS D#[43] D#[37] VSS D#[33] D#[35] VSS D#[31] D#[30] VSS D#[27] D#[24] VSS D#[23] D#[21] VSS D#[16] D#[13] VSS TEST_VTT_A82 RESERVED_A83 VSS D#[11] D#[10] VSS D#[14] D#[09] VSS D#[08] D#[05] VSS D#[03] D#[01] Signal Buffer Type Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground CMOS I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O Pull up to 2.5V Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground Pull up to VTT DO NOT CONNECT Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Pin No. B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 Pin Name DEP#[4] VCC_CORE DEP#[7] D#[62] VCC_CORE D#[58] D#[63] VCC_CORE D#[56] D#[50] VCC_CORE D#[54] D#[59] VCC_CORE D#[48] D#[52] VCC_CORE L2_SENSE VCC_CORE D#[41] D#[47] VCC_CORE D#[44] D#[36] VCC_CORE D#[40] D#[34] VCC_CORE D#[38] D#[32] VCC_CORE D#[28] D#[29] VCC_CORE D#[26] D#[25] VCC_CORE D#[22] D#[19] VCC_CORE D#[18] D#[20] VCC_CORE CORE_AN_VSENSE RESERVED_B84 VCC_CORE D#[17] D#[15] VCC_CORE D#[12] D#[07] VCC_CORE D#[06] D#[04] VCC_CORE D#[02] Signal Buffer Type AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc CMOS I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc OCVR Analog Output DO NOT CONNECT Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O 67
MECHANICAL SPECIFICATIONS
Table 50. Signal Listing in Order by Pin Number Pin No. A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121 A122 A123 A124 A125 A126 A127 A128 A129 A130 A131 A132 A133 A134 A135 A136 A137 A138 A139 A140 A141 A142 A143 A144 A145 A146 A147 A148 A149 Pin Name VSS BCLK TEST_ VSS _A98 VSS BERR# A#[33] VSS A#[34] A#[30] VSS A#[31] A#[27] VSS A#[22] A#[23] VSS A#[19] A#[18] VSS A#[16] A#[13] VSS A#[14] VSS A#[10] A#[05] VSS A#[09] A#[04] VSS RESERVED_A126 BNR# VSS BPRI# TRDY# VSS DEFER# REQ#[2] VSS REQ#[3] HITM# VSS DBSY# RS#[1] VSS BR2# BR0# VSS ADS# AP#[0] VSS VID_CORE[2] VID_CORE[1] VSS Signal Buffer Type Ground System Bus Clock Pull down to VSS Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground DO NOT CONNECT AGTL+ I/O Ground AGTL+ Input AGTL+ Input Ground AGTL+ Input AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground AGTL+ I/O AGTL+ Input Ground AGTL+ Input AGTL+ I/O Ground AGTL+ I/O AGTL+ I/O Ground Open or Short to VSS Open or Short to VSS Ground Pin No. B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 B122 B123 B124 B125 B126 B127 B128 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140 B141 B142 B143 B144 B145 B146 B147 B148 B149 Pin Name D#[00] VCC_CORE RESET# N/C VCC_CORE A#[35] A#[32] VCC_CORE A#[29] A#[26] VCC_L2 A#[24] A#[28] VCC_L2 A#[20] A#[21] VCC_L2 A#[25] A#[15] VCC_L2 A#[17] A#[11] VCC_L2 A#[12] VCC_L2 A#[08] A#[07] VCC_L2 A#[03] A#[06] VCC_L2 AERR# REQ#[0] VCC_L2 REQ#[1] REQ#[4] VCC_L2 LOCK# DRDY# VCC_L2 RS#[0] HIT# VCC_L2 RS#[2] RP# VCC_L2 BR3# BR1# VCC_L2 RSP# AP#[1] VCC_L2 WP VID_CORE[3] Signal Buffer Type AGTL+ I/O Cartridge Vcc AGTL+ Input Cartridge Vcc AGTL+ I/O AGTL+ I/O Cartridge Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ I/O AGTL+ I/O L2 Cache Vcc AGTL+ Input AGTL+ I/O L2 Cache Vcc AGTL+ Input AGTL+ I/O L2 Cache Vcc AGTL+ Input AGTL+ Input L2 Cache Vcc AGTL+ Input AGTL+ I/O L2 Cache Vcc SMBus Input Open or Short to VSS 68
MECHANICAL SPECIFICATIONS
Table 50. Signal Listing in Order by Pin Number Pin No. A150 A151 A152 A153 A154 A155 A156 A157 A158 A159 A160 A161 A162 A163 A164 A165 Pin Name VID_CORE[4] SMBALERT# VSS VID_L2[2] VID_L2[1] VSS VTT VTT VSS SA2 VCC_SM VSS SA1 SA0 VSS PWR_EN[0] Signal Buffer Type Open or Short to VSS SMBus Alert Ground Open or Short to VSS Open or Short to VSS Ground AGTL+ VTT Supply AGTL+ VTT Supply Ground SMBus Input SMBus Supply Ground SMBus Input SMBus Input Ground Short to PWR_EN[1] Pin No. B150 B151 B152 B153 B154 B155 B156 B157 B158 B159 B160 B161 B162 B163 B164 B165 Pin Name VCC_L2 VID_CORE[0] VID_L2[0] VCC_L2 VID_L2[4] VID_L2[3] VCC_L2 VTT VTT VCC_L2 SMBCLK SMBDAT VCC_L2 RESERVED_B163 RESERVED_B164 RESERVED_B165 Signal Buffer Type L2 Cache Vcc Open or Short to VSS Open or Short to VSS L2 Cache Vcc Open or Short to VSS Open or Short to VSS L2 Cache Vcc AGTL+ VTT Supply AGTL+ VTT Supply L2 Cache Vcc SMBus Clock SMBus Data L2 Cache Vcc DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT
69
MECHANICAL SPECIFICATIONS
Table 51. Signal Listing in Order by Pin Name
Pin No. B124 A124 A121 B125 B122 B121 A123 A120 B117 B119 A116 A118 B114 A115 B116 A113 A112 B110 B111 A109 A110 B107 B113 B105 A107 B108 B104 A104 A106 B102 A101 A103 B101 A14 A144 B127 A145 B146 A97 A100 A35 A127 B33 A32 A33 B37 A129 A142 B143 A141 B142 B83 B96 A95 B95 A94
Pin Name A#[03] A#[04] A#[05] A#[06] A#[07] A#[08] A#[09] A#[10] A#[11] A#[12] A#[13] A#[14] A#[15] A#[16] A#[17] A#[18] A#[19] A#[20] A#[21] A#[22] A#[23] A#[24] A#[25] A#[26] A#[27] A#[28] A#[29] A#[30] A#[31] A#[32] A#[33] A#[34] A#[35] A20M# ADS# AERR# AP#[0] AP#[1] BCLK BERR# BINIT# BNR# BP#[2] BP#[3] BPM#[0] BPM#[1] BPRI# BR0# BR1# BR2# BR3# CORE_AN_VSENSE D#[00] D#[01] D#[02] D#[03]
Signal Buffer Type AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O CMOS Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O System Bus Clock AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O AGTL+ Input AGTL+ Input AGTL+ Input OCVR Analog Output AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O 70
MECHANICAL SPECIFICATIONS
Pin No. B93 A92 B92 B90 A91 A89 A86 A85 B89 A80 A88 B87 A79 B86 B80 B78 B81 A77 B77 A76 A74 B75 B74 A73 B71 B72 A71 A70 B69 A67 B66 A68 B63 A65 B68 A61 B65 B59 A58 A64 B62 A59 A51 B60 B54 A53 B49 A54 B55 A48 B51 A45 B48 A50 B45 B52 A47 A44 B43 B46 Pin Name D#[04] D#[05] D#[06] D#[07] D#[08] D#[09] D#[10] D#[11] D#[12] D#[13] D#[14] D#[15] D#[16] D#[17] D#[18] D#[19] D#[20] D#[21] D#[22] D#[23] D#[24] D#[25] D#[26] D#[27] D#[28] D#[29] D#[30] D#[31] D#[32] D#[33] D#[34] D#[35] D#[36] D#[37] D#[38] D#[39] D#[40] D#[41] D#[42] D#[43] D#[44] D#[45] D#[46] D#[47] D#[48] D#[49] D#[50] D#[51] D#[52] D#[53] D#[54] D#[55] D#[56] D#[57] D#[58] D#[59] D#[60] D#[61] D#[62] D#[63] Signal Buffer Type AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O 71
MECHANICAL SPECIFICATIONS
Pin No. A138 A132 A36 A38 B39 A39 B40 A41 A42 B42 B134 A15 B10 B99 B137 A136 A3 A12 A17 B13 A27 B28 B133 B57 B3 A26 B30 A29 B31 B36 A30 A165 B1 A21 B128 B130 A133 A135 B131 A1 A11 A126 B163 B164 B165 B22 B24 B25 B34 B84 B9 B98 B140 B136 A139 B139 B145 A163 A162 Pin Name DBSY# DEFER# DEP#[0] DEP#[1] DEP#[2] DEP#[3] DEP#[4] DEP#[5] DEP#[6] DEP#[7] DRDY# FERR# FLUSH# N/C HIT# HITM# HV_EN# IERR# IGNNE# INIT# LINT[0] LINT[1] LOCK# L2_SENSE OCVR_OK OCVR_EN PICCLK PICD[0] PICD[1] PRDY# PREQ# PWR_EN[0] PWR_EN[1] PWRGOOD REQ#[0] REQ#[1] REQ#[2] REQ#[3] REQ#[4] RESERVED_A1 RESERVED_A11 RESERVED_A126 RESERVED_B163 RESERVED_B164 RESERVED_B165 RESERVED_B22 RESERVED_B24 RESERVED_B25 RESERVED_B34 RESERVED_B84 RESERVED_B9 RESET# RP# RS#[0] RS#[1] RS#[2] RSP# SA0 SA1 Signal Buffer Type AGTL+ I/O AGTL+ Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O CMOS Output CMOS Input AGTL+ I/O AGTL+ I/O OPEN (2.8V version) SHORT (5V/12V version) CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input AGTL+ I/O CMOS I/O Open Drain Output CMOS INPUT APIC Clock Input CMOS I/O CMOS I/O AGTL+ Output CMOS Input Short to PWR_EN[1] Short to PWR_EN[0] CMOS Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT AGTL+ Input AGTL+ I/O AGTL+ Input AGTL+ Input AGTL+ Input AGTL+ Input SMBus Input SMBus Input 72
MECHANICAL SPECIFICATIONS
Pin No. A159 A9 A7 B18 A151 B160 B161 B12 B15 B16 A18 A20 A23 A62 B27 A98 B4 A82 A24 B19 A130 B21 B100 B103 B11 B14 B17 B2 B20 B23 B26 B29 B32 B35 B38 B41 B44 B47 B5 B50 B53 B56 B58 B61 B64 B67 B70 B73 B76 B79 B8 B82 B85 B88 B91 B94 B97 B106 B109 Pin Name SA2 SELFSB0 SELFSB1 SLP# SMBALERT# SMBCLK SMBDAT SMI# STPCLK# TCK TDI TDO TEST_2.5_A23 TEST_2.5_A62 TEST_2.5_B27 TEST_VSS_A98 TEST_VSS_B4 TEST_VTT_A82 THERMTRIP# TMS TRDY# TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_L2 (N/C) VCC_L2 (N/C) Signal Buffer Type SMBus Input CMOS Input CMOS Output CMOS Input SMBus Alert SMBus Clock SMBus I/O CMOS Input CMOS Input TAP Clock TAP Input TAP Output Pull up to 2.5V Pull up to 2.5V Pull up to 2.5V Pull down to VSS Pull down to VSS Pull up to VTT CMOS Output TAP Input AGTL+ Input TAP Input Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc Cartridge Vcc L2 Cache Vcc L2 Cache Vcc 73
MECHANICAL SPECIFICATIONS
Pin No. B112 B115 B118 B120 B123 B126 B129 B132 B135 B138 B141 B144 B147 B150 B153 B156 B159 B162 A160 A2 A56 B151 A148 A147 B149 A150 B152 A154 A153 B155 B154 A10 A102 A105 A108 A111 A114 A117 A119 A122 A125 A128 A13 A131 A134 A137 A140 A143 A146 A149 A152 A155 A158 A16 A161 A164 A19 A22 A25 Pin Name VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_L2 (N/C) VCC_SM VCC_TAP VIN_SENSE VID_CORE[0] VID_CORE[1] VID_CORE[2] VID_CORE[3] VID_CORE[4] VID_L2[0] VID_L2[1] VID_L2[2] VID_L2[3] VID_L2[4] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal Buffer Type L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc L2 Cache Vcc SMBus Supply TAP Supply CMOS I/O Open or Short to VSS Open or Short to VSS Open or Short to VSS Open or Short to VSS Open or Short to VSS Open or Short to VSS Open or Short to VSS Open or Short to VSS Open or Short to VSS Open or Short to VSS Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground 74
MECHANICAL SPECIFICATIONS
Pin No. A28 A31 A34 A37 A4 A40 A43 A46 A49 A52 A55 A57 A60 A63 A66 A69 A72 A75 A78 A8 A81 A84 A87 A90 A93 A96 A99 A156 A157 A5 A6 B157 B158 B6 B7 B148 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT VTT VTT VTT VTT VTT VTT WP Signal Buffer Type Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground AGTL+ VTT Supply AGTL+ VTT Supply AGTL+ VTT Supply AGTL+ VTT Supply AGTL+ VTT Supply AGTL+ VTT Supply AGTL+ VTT Supply AGTL+ VTT Supply SMBus Input
75
INTEGRATION TOOLS
8. INTEGRATION TOOLS
The integration tool set for system designs will include an In-Target Probe (ITP) for program execution control, register/memory/IO access, and breakpoint control. This tool provides functionality commonly associated with debuggers and emulators. The ITP uses the on-chip debug features of the processor to provide program execution control. Use of the ITP will not affect the high-speed operations of the processor signals, ensuring the system can operate at full speed with the ITP attached. This document describes the ITP as well as a number of technical issues that must be taken into account when including the ITP and logic analyzer interconnect tools in a debug strategy. Although the tool description that follows is specific to early tools available from Intel, similar tools may also be provided in the future by third-party vendors. Thus, the tools mentioned should not be considered as Intel's tools, but as debug tools in the generic sense. In general, the information in this chapter may be used as a basis for including integration tools in any Pentium(R) III XeonTM processor at 700 MHz and 900 MHz-based system design. The logic analyzer interconnect tool keep-out zones described in this chapter should be used as general guidelines for Pentium(R) III XeonTM processor at 700 MHz and 900 MHz system design.
8.1 In-Target Probe (ITP)
An In-Target Probe (ITP) for the processor is a debug tool that allows access to on-chip debug features via a small port on the system board called the debug port. The ITP communicates to the processor through the debug port using a combination of hardware and software. The software is a Microsoft* Windows* NT* 4.0based application running on a host PC. The hardware consists of a PCI board in the host PC connected to the signals that make up the processor debug interface. Due to the nature of the ITP, the processor may be controlled without affecting any high-speed signals. This ensures that the system can operate at full speed with the ITP attached. Intel will use an ITP for internal debug and system validation and recommends that all Pentium(R) III XeonTM processor at 700 MHz and 900 MHz-based system designs include a debug port. This is especially important if Intel assistance is required in debugging a system-processor interrelationship issue. 8.1.1 PRIMARY FUNCTION The primary function of an ITP is to provide a control and query interface for one or more processors. With an ITP, one can control program execution and have the ability to access processor registers, system memory and I/O. Thus, one can start and stop program execution using a variety of breakpoints, single-step the program at the assembly code level, as well as read and write registers, memory and I/O. The on-chip debug features will be controlled from a Microsoft* Windows* NT* 4.0 software application running on a Pentium(R) or Pentium(R) Pro processor-based PC with a PCI card slot (See Figure 29).
PCI Add-In Card
Plugs in to your host PC (12.5 in.)
2m Cable
2 in. Cable
Debug Port Connector
Connects to Debug Port on target board
Buffer Board
000816a
Figure 29. Hardware Components of the ITP
8.1.2 DEBUG PORT CONNECTOR DESCRIPTION
76
INTEGRATION TOOLS
The ITP will connect to the system through the debug port. Recommended connectors, to mate the ITP cable with the debug port on the board, are available in either a vertical or right angle configuration. Both configurations fit into the same board footprint. The connectors are manufactured by AMP Incorporated and are in the AMPMODU System 50 line. Following are the AMP part numbers for the two connectors: * * Amp 30-pin shrouded vertical header: 104068-3 Amp 30-pin shrouded right-angle header: 104069-5 NOTE These are high density through hole connectors with pins on 0.050 in. by 0.100 in. centers. Do not confuse these with the more common 0.100 in. by 0.100 in. center headers. The debug port must be mounted on the system baseboard; the processor does not contain a debug port. 8.1.3 KEEP OUT CONCERNS Two keep out concerns need to be taken into account when designing a system that will support an ITP. First, system designers need to be aware that in order for the ITP cabling to egress the system under test, they must either remove the "skins" of the system under test, or, when this is not possible, design an aperture into the system. Secondly, keep out regions will be required around the debug port connector. See Figure 30 for the keep out region required for the processor.
TOP VIEW OF DEBUG PORT CONNECTOR WITH COMPONENT KEEP OUT AREA PROJECTION
Figure 30. Debug Port Connector Keep Out Region
8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS Please contact your Integration Tools vendor for any additional mechanical keep out restrictions for the system design. 8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS Table 52 describes the debug port signals and provides the pin assignment. Table 52. Debug Port Pinout Description and Requirements1
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INTEGRATION TOOLS
Name RESET# Pin 1 Description Reset signal from MP cluster to ITP. Specification Requirement Terminate2 signal properly at the debug port. Notes Connected to high-speed comparator (biased at 2/3 of the level found at the POWERON pin) on the ITP buffer board. Additional load does not change timing calculations for the processor bus agents if routed properly. Open drain output from ITP to the target system. It will be held asserted for 100 ms; capacitance needs to be small enough to recognize assert. The pull-up resistor should be picked to (1) meet VIL of target system and (2) meet specified rise time. Poor routing can cause multiple clocking problems. Should be routed to all components in the boundary scan chain3. Simulations should be run to determine the proper value for series termination or Bessel filter, see figure 31. Operates synchronously with TCK. Should be routed to all components in the boundary scan chain3. Simulations should be run to determine the proper value for series termination.
Debug port must be at the end of the signal trace.
DBRESET#
3
Allows ITP to reset entire target system.
Tie signal to target system reset (recommendation): PWR_OK signal on PCIset as an ORed input). Pulled-up signal with the proper resistor (see Signal Notes section, following).
TCK
5
The TAP (Test Access Port) clock from ITP to MP cluster.
Add 1.0K pull-up resistor to Vcc_TAP near driver. For MP systems, each processor should receive a separately buffered TCK. Add a series termination resistor or a Bessel filter on each output.
TMS
7
Test mode select signal from ITP to MP cluster, controls the TAP finite state machine.
Add 1.0 K pull-up resistor to Vcc_TAP near driver. For MP systems, each processor should receive a separately buffered TMS. Add a series termination resistor on each output.
TDI
8
Test data input signal from ITP to first component in boundary scan chain of MP cluster; inputs test instructions and data serially.
This signal is open-drain from the ITP. However, TDI is pulled up to Vcc_TAP with ~150 on the processor. Add a 150 to 330 pull-up resistor (to Vcc_TAP) if TDI will not be connected directly to a processor. Add 1.5K pull-up resistor (to VTT).
Operates synchronously with TCK.
POWERON
9
Used by ITP to determine when target system power is ON and, once target system is ON, enables all debug port electrical interface activity. From target VTT to ITP. Test data output signal from last component in boundary scan chain of MP cluster to ITP; test output is read serially. Indicates to target system that the ITP is installed. Test reset signal from ITP to MP cluster, used to reset TAP logic.
If no power is applied, the ITP will not drive any signals; isolation provided using isolation gates. Voltage applied is internally used to set AGTL+ threshold (or reference) at 2/3 VTT.
TDO
10
Add 150 pull-up resistor (to Vcc_TAP). Design pull-ups to route around empty processor sockets (so resistors are not in parallel). Add ~10K pull-up resistor.
Operates synchronously with TCK. Each processor has a 25 driver.
DBINST#
11
Not required if boundary scan is not used in target system. Asynchronous input signal.
TRST#
12
Add ~680 pull-down. To disable TAP reset if ITP not installed.
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Table 52. Debug Port Pinout Description and Requirements1
Name BSEN# Pin 14 Description Informs target system that ITP is using boundary scan. PREQ0# signal, driven by ITP, makes requests to P0 to enter debug. PRDY0# signal, driven by P0, informs ITP that P0 is ready for debug. Add 150 to 330 pull-up resistor (to Vcc_TAP). Terminate2 signal properly at the debug port. Debug port must be at the end of the signal trace. Specification Requirement Notes Not required if boundary scan is not used in target system.
PREQ0#
16
PRDY0#
18
Connected to high-speed comparator (biased at 2/3 of the level found at the POWERON pin) on the ITP buffer board. Additional load does not change timing calculations for the processor bus agents if routed properly.
PREQ1#
20
PREQ1# signal from ITP to P1. PRDY1# signal from P1 to ITP.
Add 150 to 330 pull-up resistor (to Vcc_TAP) Terminate2 signal properly at the debug port. Debug port must be at the end of the signal trace. Connected to high-speed comparator (biased at 2/3 of the level found at the POWERON pin) on the ITP buffer board. Additional load does not change timing calculations for the processor bus agents.
PRDY1#
22
PREQ2#
24
PREQ2# signal from ITP to P2. PRDY2# signal from ITP to P2.
Add 150 to 330 pull-up resistor (to Vcc_TAP). Terminate2 signal properly at the debug port. Debug port must be at the end of the signal trace. Connected to high-speed comparator (biased at 2/3 of the level found at the POWERON pin) on the ITP buffer board. Additional load does not change timing calculations for the processor bus agents if routed properly.
PRDY2#
26
PREQ3#
28
PREQ3# signal from ITP to P3. PRDY3# signal from ITP to P3.
Add 150 to 330 pull-up resistor (to Vcc_TAP). Terminate2 signal properly at the debug port. Debug port must be at the end of the signal trace. Connected to high-speed comparator (biased at 2/3 of the level found at the POWERON pin) on the ITP buffer board. Additional load does not change timing calculations for the processor bus agents if routed properly. A separate driver should be used to avoid loading issues associated with having the ITP either installed or not installed.
PRDY3#
30
BCLK
29
Bus clock from the MP cluster.
Use a separate driver to drive signal to the debug port.
GND
2, 4, 6, 13, 15, 17, 19, 21, 23, 25, 27
Signal ground.
Connect all pins to signal ground.
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NOTES:
1. 2. 3. Resistor values with "~" preceding them can vary from the specified value; use resistor as close as possible to the value specified. Termination should include series (~240) and AGTL+ termination (connected to 1.5V) resistors. See Figure 30A. Signal should be at end of daisy chain and the boundary scan chain should be partitioned into two distinct sections to assist in debugging the system: one partition with only the processor(s) for system debug (i.e., used with the ITP) and another with all other components for manufacturing or system test.
8.1.6 DEBUG PORT SIGNAL NOTES In general, all open drain AGTL+ outputs from the system must be retained at a proper logic level, whether or not the debug port is installed. RESET# from the processor system should be terminated at the debug port, as shown in Figure 30A. Rt should be a 150 on RESET#. PRDYn# should have a similar layout, however Rt should be 50 to match board impedance rather than the normal 150 since there are only 2 loads on this signal.
Figure 30A. AGTL+ Signal Termination
8.1.6.1 General Signal Quality Notes Signals from the debug port are fed to the system from the ITP via a buffer board and a cable. If system signals routed to the debug port (i.e. TDO, PRDYn# and RESET#) are used elsewhere in the system, then dedicated drivers should be used to isolate the signals from reflections coming from the end of this cable. If the processor boundary scan signals are used elsewhere in the system, then the TDI, TMS, TCK, and TRST# signals from the debug port should be isolated from the system signals. In general, no signals should be left floating. Thus, signals going from the debug port to the processor system should not be left floating. If they are left floating, there may be problems when the ITP is not plugged into the connector. 8.1.6.2 Signal Note: DBRESET# The DBRESET# output signal from the ITP is an open drain with about 5 of RDS. The usual implementation is to connect it to the PWROK open drain signal on the PCIset components as an OR input to initiate a system reset. In order for the DBRESET# signal to work properly, it must actually reset the entire target system. The signal should be pulled up (Intel recommends a 240 resistor, but system designers will need to fine tune specific system designs) to meet two considerations: (1) the signal must be able to meet VIL of the system, and (2) it must allow the signal to meet the specified rise time. When asserted by the ITP, the DBRESET# signal will remain asserted for 100 ms. A large capacitance should not be present on this signal as it may prevent a full charge from building up within 100 ms. 8.1.6.3 Signal Note: TDO and TDI
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The TDO signal of each processor has a 2.5V Tolerant open-drain driver. The TDI signal of each processor contains a 150 pull-up to VccTAP. When connecting one processor to the next, or connecting to the TDI of the first processor, no external pull-up is required. However, the last processor of the chain does require a pull-up before passing the signal to the next device in the chain. 8.1.6.4 Signal Note: TCK and TMS WARNING A significant number of target systems have had signal integrity issues with the TCK signal. TCK is a critical clock signal and must be routed accordingly; make sure to observe power and ground plane integrity for this signal. Follow the guidelines below and assure the quality of the signal when beginning use of an ITP to debug your target. Due to the number of loads on the TCK signal, special care should be taken when routing this. Poor routing can lead to multiple clocking of some agents on the debug chain, usually on the falling edge of TCK. This causes information to be lost through the chain and can result in bad commands being issued to some agents on the chain. Systems using other TCK routing schemes, particularly those with `T' or `Y' configurations where the trace from the source to the `T' is long, could have signal integrity problems. The suggested routing scheme is to drive each of the agent TCK signals individually from a buffer device. Figure 31 shows how the TCK signal should be routed to the agents in a 4-way Pentium(R) III XeonTM processor-based system incorporating the Intel(R) 450NX PCIset. A Bessel filter is recommended over a series termination at the output of each buffer. The values shown in Figure 31 are only examples. The designer should determine the LC values appropriate for their particular application. If it is desired to ship production systems without the 2.5V buffers installed, then pull-up resistors should be placed at the outputs to prevent TCK from floating.
SC330.1 0
SC330.1 1
SC330.1 2
SC330.1 3
2.5V Buffers 74LVQ244 Type 2.5V Pull up Resistor 100 nH 100 nH 100 nH 100 nH 100 nH Debug Port 100 nH
56 pF 56 pF 56 pF 56 pF 56 pF 56 pF To each device, other JTAG ...
TCK
Figure 31. TCK with individual buffering scheme
The ITP buffer board drives the TCK signal through the debug port, to the buffered device(s). 81
INTEGRATION TOOLS
NOTE The buffer rise and fall edge rates should NOT be FASTER than 3nS. Edge rates faster than this in the system can contribute to signal reflections that endanger ITP compatibility with the target system. A low voltage buffer capable of driving 2.5V outputs such as an 74LVQ244 is suggested to eliminate the need for attenuation. Simulation should be performed to verify that the edge rates of the buffer chosen are not too fast. The pull-up resistor to 2.5V keeps the TCK signal from floating when the ITP is not connected. The value of this resistor should be such that the ITP can still drive the signal low (1K). The trace lengths from the buffer to each of the agents should also be kept at a minimum to ensure good signal integrity. 8.1.7 Using the TAP to Communicate to the processor An ITP communicates to the processor by stopping their execution and sending/receiving messages over boundary scan pins. As long as each processor is tied into the system boundary scan chain, the ITP can communicate with it. In the simplest case, the processors are back to back in the scan chain, with the boundary scan input (TDI) of the first processor connected up directly to the pin labeled TDI on the debug port and the boundary scan output of the last processor connected up to the pin labeled TDO on the debug port as shown in Figure 32.
V CC
TAP
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
SC 330.1 Processor
SC 330.1 Processor
SC 330.1 Processor
SC 330.1 Processor
TDI TDO TDI TDO TDI Note: See previous table for recommended pull-up resistor values.
TDO
Debug Port (ITP)
PCIset Component
PCIset Component
000799c
000799c
Figure 32. System Preferred Debug Port Layout
8.2 Logic Analyzer Interconnect (LAI) and Trace Capture Tool Considerations
8.2.1 LAI and Trace Capture Tool System Design Considerations System designers must contact their third party tools vendors for Logic Analyzer Interface design considerations for the processor including electrical load models for system simulations. At this time, HewlettPackard, Tektronix, and American Arium are currently investigating Logic Analyzer Interconnect or trace capture tools for the processor. 8.2.2 LAI and Trace Capture tool Mechanical Keep Outs Please contact your third party tools vendor for mechanical keep out restrictions for the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz.
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9. BOXED PROCESSOR SPECIFICATIONS 9.1 Introduction
The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz is also offered as an Intel(R) boxed processor. Intel(R) boxed processors are intended for system integrators who build systems from baseboards and off-theshelf components. The boxed Pentium(R) III XeonTM processor at 700 MHz and 900 MHz is supplied with an attached passive heatsink. This section documents baseboard and system requirements for the heatsink that will be supplied with the boxed processor. This section is particularly important for OEMs that manufacture baseboards for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in inches. Figure 33 shows a mechanical representation of the boxed Pentium(R) III XeonTM processor at 700 MHz and 900 MHz.
Figure 33. Boxed Pentium(R) III XeonTM Processor at 700 MHz and 900 MHz
9.2 Mechanical Specifications
This section documents the mechanical specifications of the boxed Pentium(R) III XeonTM processor at 700 MHz and 900 MHz heatsink. The boxed processor ships with an attached passive heatsink. Clearance is required around the heatsink to ensure proper installation of the processor and unimpeded airflow for proper cooling. The space requirements and dimensions for the boxed processor are shown in Figure 34 (Side View), Figure 35 (Front View), and Table 53. All dimensions are in inches.
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BOXED PROCESSOR SPECIFICATIONS
A C
D
B
Figure 34. Side View Space Requirements for the Boxed Processor
84
BOXED PROCESSOR SPECIFICATIONS
F
E
Figure 35. Front View Space Requirements for the Boxed Processor
9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS Table 53. Boxed Processor Heatsink Dimensions Fig. Ref. Label A B C D E F Dimensions (Inches) Heatsink Depth (off heatsink attach point) Heatsink Height (above baseboard) Heatsink Base Thickness Heatsink Total Height at Fins Heatsink Total Height at Base (see front view) Heatsink Width (see front view) 4.065 4.235 5.05 0.485 0.200 Min Typ 1.03 Max
9.2.2 BOXED PROCESSOR HEATSINK WEIGHT The boxed processor heatsink will not weigh more than 350 grams (without auxiliary fan). 9.2.3 BOXED PROCESSOR RETENTION MECHANISM The boxed Pentium(R) III XeonTM processor at 700 MHz and 900 MHz requires a retention mechanism that supports and secures the Single Edge Contact Cartridge (S.E.C.C.) in the 330-contact slot connector. An S.E.C.C. retention mechanism is not provided with the boxed processor. Baseboards designed for use by system integrators should include a retention mechanism and appropriate installation instructions. The boxed
85
BOXED PROCESSOR SPECIFICATIONS
processor does not require additional heatsink supports. processor. Heatsink supports are not shipped with the boxed
9.3 Thermal Specifications
This section describes the cooling requirements of the heatsink solution utilized by the boxed processor. 9.3.1 Boxed Processor Cooling Requirements The boxed processor passive heatsink requires airflow horizontally across the heatsink to cool the processor. The boxed processor heatsink will keep the processor thermal plate temperature, TPLATE, within the specification, provided adequate airflow is directed into the system chassis, across the heatsink and out of the system chassis. System integrators should perform thermal testing using thermocouples (see the section entitled Processor Thermal Analysis) to evaluate the thermal efficiency of the system. 9.3.2 Boxed Processor Passive Heatsink Performance The boxed processor's passive heatsink is designed to provide effective heat transfer between the processor package thermal plate and the air immediately surrounding the heatsink. The direction and temperature of air flowing across the heatsink variably affects the efficiency of the heatsink. Figure 36 shows the thermal efficiency of the boxed processor heatsink, using three different directions of airflow: horizontal, top-down, and normal to the plane of the thermal plate. The performance characterization was completed in a wind tunnel, using a processor running at maximum power and at maximum thermal specification. The characterization assumes that air entering the heatsink is at constant temperature and uniformly traverses the heatsink, and that heated air is evacuated from the chassis and is not re-circulated. The characterization also assumes natural obstructions, such as the motherboard in a top-down airflow model. To determine if a particular chassis has appropriate airflow to effectively cool the processor, measure the "upstream" temperature (TAMBIENT, the ambient air temperature within the chassis) and the velocity of the air entering the heatsink. The Y-axis in Figure 36 represents the thermal resistance ( PA) and the X-axis represents the airflow speed in linear feet per minute (lfm). PA can be calculated as the difference between the thermal plate temperature and ambient air temperature (within the chassis) divided by the processor's maximum power specification.
PA =
T PLATE - T AMBIENT P MAX
To determine if your airflow is adequate, determine the airflow speed and direction, and identify the appropriate curve in Figure 36. Calculate PA and determine if it falls below the graphed line at the appropriate airflow speed.
1.5 1.4 1.3 1.2 1.1
PA
Horizontal Normal Top-Down Aux. Fan (50mm)
1 0.9 0.8 0.7 0.6 0.5 0.4 100 150 200 250 300 350 400
Airflow Speed (lfm)
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Figure 36. Boxed Processor Heatsink Performance
Figure 36 also shows the performance of the boxed processor heatsink with an attached auxiliary fan (50mm X 50mm X 15mm). In this case, the temperature of the air entering the fan is used as TAMBIENT. TAMBIENT is measured just outside the fan's air intake. The presence of the auxiliary fan allows the cooling solution to perform with very little local airflow. Therefore, PA is virtually constant and independent of the speed and direction of airflow across the heatsink. 9.3.2 Optional auxiliary fan attachment The boxed processor's passive heatsink includes features that allow for attachment of an auxiliary fan to improve airflow over the passive heatsink. A typical 40mm, 50mm, or 60mm fan can be attached. System integrators must evaluate the thermal performance of their system (see above) and consider the baseboard manufacturer's recommendations for thermal management before deciding if an auxiliary fan is warranted. If an auxiliary fan is needed (e.g. for the front processor in a multiprocessor system), it may be attached to the face of the boxed processor's passive heatsink. To facilitate this, the boxed processor's passive heatsink will include features in the heatsink fins onto which fan mounting hardware can be attached. The appropriate fan attach hardware will be included with the boxed Pentium(R) III XeonTM processor at 700 MHz and 900 MHz if necessary. The boxed Pentium(R) III XeonTM processor at 700 MHz and 900 MHz does not ship with an auxiliary fan.
Figure 37. Conceptual Views of the Boxed Processor with Attached 40mm and 50mm Auxiliary Fan (fan not included with the Boxed Processor).
9.3.2.1 Clearance recommendations for auxiliary fan If an auxiliary fan is used, clearance must be provided in front of the boxed processor passive heatsink to accommodate the mechanical and airflow clearance requirements of the fan and mounting hardware. Baseboard-mounted components and chassis members should not violate the clearance requirements for the auxiliary fan. Figure 38 and Figure 39 show the clearance recommended for the fan and air inlet. Required airspace clearance for fans may vary by manufacturer. Consult your fan manufacturer and/or fan documentation for specifications.
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BOXED PROCESSOR SPECIFICATIONS
4.24
1.5
Figure 38. Side View Space Recommendation for the Auxiliary Fan
Figure 39. Front View Space Recommendation for the Auxiliary Fan
9.3.2.2 Fan power recommendations for auxiliary fan To facilitate power to the auxiliary fan and provide fan monitoring, a fan-sense capable power header may be provided on the baseboard near every processor that may need an auxiliary fan. Although the boxed 88
BOXED PROCESSOR SPECIFICATIONS
processor does not ship with an auxiliary fan, it is highly recommended that a power header be provided. It is also recommended that the power header be consistent with the power header for other boxed processors that feature a fan-sense capable fan heatsink. Figure 40 shows the typical boxed processor fan/heatsink power cable connector. Table 54 shows the typical boxed processor fan power cable connector requirements. The actual requirements for the auxiliary fan power may vary. Consult your fan manufacturer and/or fan documentation for specifications.
Pin 1 2 3
Signal GND +12V SENSE Straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. Waldom*/Molex* P/N 22-01-3037 or equivalent. Match with straight pin, friction lock header on motherboard Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3, or equivalent.
1
2
3
000888
Figure 40. Standard Boxed Processor Fan/Heatsink Power Cable Connector Description
Table 54. Fan/Heatsink Power and Signal Specifications Description +12V: 12 volt fan power supply IC: Fan current draw SENSE: SENSE frequency (baseboard should pull this pin up to appropriate VCC with resistor (typically 10 to 12 k) Min 7V Typ 12V 100mA 2 pulses per fan revolution Max 13.8V
9.3.2.3 Thermal evaluation for auxiliary fan Given the complex and unique nature of baseboard layouts, and the special chassis required to support them, thermal performance may vary greatly with each baseboard/chassis combination. Baseboard manufacturers must evaluate and recommend effective thermal solutions for their specific designs, particularly designs that are proprietary. Such thermal solutions must take all system components into account. The power requirements of all processors that will be supported by the baseboard should be accommodated. The boxed Pentium(R) III XeonTM processor at 700 MHz and 900 MHz is designed to provide a flexible cooling solution by incorporating features by which an auxiliary fan may be attached. Should the system thermal evaluation warrant the requirement for an auxiliary fan, an auxiliary fan must be included with the baseboard to allow the thermal requirements of the system to be met.
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10. APPENDIX
This appendix provides an alphabetical listing of all Pentium(R) III XeonTM processor at 700 MHz and 900 MHz signals and tables that summarize the signals by direction: output, input, and I/O.
10.1 Alphabetical Signals Reference
This section provides an alphabetical listing of all processor signals. 10.1.1 A[35:03]# (I/O) The A[35:3]# (Address) signals define a 236-byte physical memory address space. When ADS# is active, these pins transmit the address of a transaction; when ADS# is inactive, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the processor system bus. The A[35:24]# signals are parityprotected by the AP1# parity signal, and the A[23:03]# signals are parity protected by the AP0# parity signal. On the active-to-inactive transition of RESET#, the processors sample the A[35:03]# pins to determine their power-on configuration. See the Pentium II Processor Developer's Manual for details. 10.1.2 A20M# (I) If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction. During active RESET#, each processor begins sampling the A20M#, IGNNE#, and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See Figure 1. On the active-to-inactive transition of RESET#, each processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals for normal operation.
10.1.3 ADS# (I/O) The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction address on the A[35:03]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must connect the appropriate pins on all processor system bus agents.
10.1.4 AERR# (I/O) The AERR# (Address Parity Error) signal is observed and driven by all processor system bus agents, and if used, must connect the appropriate pins on all processor system bus agents. AERR# observation is optionally enabled during poweron configuration; if enabled, a valid assertion of AERR# aborts the current transaction. If AERR# observation is disabled during power-on configuration, a central agent may handle an assertion of AERR# as appropriate to the Machine Check Architecture (MCA) of the system.
10.1.5 AP[1:0]# (I/O) The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#, A[35:03]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers A[23:03]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all processor system bus agents. 10.1.6 BCLK (I)
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APPENDIX
The BCLK (Bus Clock) is a 2.5V tolerant signal that determines the bus frequency. All processor system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters are specified with respect to the BCLK signal. 10.1.7 BERR# (I/O) The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents, and must connect the appropriate pins of all such agents, if used. However, the processor does not observe assertions of the BERR# signal. BERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options:
* * * *
Enabled or disabled. Asserted optionally for internal errors along with IERR#. Asserted optionally by the request initiator of a bus transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus transaction.
10.1.8 BINIT# (I/O) The BINIT# (Bus Initialization) signal may be observed and driven by all processor system bus agents, and if used must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information. If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state machines are reset and any data which was in transit is lost. All agents reset their rotating ID for bus arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches are not affected. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the Machine Check Architecture (MCA) of the system. 10.1.9 BNR# (I/O) The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must connect the appropriate pins of all processor system bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges. 10.1.10 BP[3:2]# (I/O) The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the status of breakpoints. 10.1.11 BPM[1:0]# (I/O) The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. 10.1.12 BPRI# (I) The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of all processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.
10.1.13 BR0# (I/O), BR[3:1]# (I)
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The BR[3:1]# (Bus Request) pins drive the BREQ[3:0]# signals on the system. The BR[3:0]# pins are interconnected in a rotating manner to other processors' BR[3:0]# pins. Table 55 gives the rotating interconnect between the processor and bus signals for 4-way processor-based systems.
Table 55. BR[3:0]# Signals Rotating Interconnect, 4-Way system Bus Signal BREQ0# BREQ1# BREQ2# BREQ3# Agent 0 Pins BR0# BR1# BR2# BR3# Agent 1 Pins BR3# BR0# BR1# BR2# Agent 2 Pins BR2# BR3# BR0# BR1# Agent 3 Pins BR1# BR2# BR3# BR0#
Table 56 gives the interconnect between the processor and bus signals for a 2-way processor-based system. Table 56. BR[3:0]# Signals Rotating Interconnect, 2-Way system Bus Signal BREQ0# BREQ1# BREQ2# BREQ3# Agent 0 Pins BR0# BR1# N/C N/C Agent 1 Pins BR3# BR0# N/C N/C
During power-up configuration, the central agent must assert its BR0# signal. All symmetric agents sample their BR[3:0]# pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent ID. All agents then configure their BREQ[3:0]# signals to match the appropriate bus signal protocol, as shown in Table 57. Table 57. Agent ID Configuration BR0# L H H H BR1# H H H L BR2# H H L H BR3# H L H H Agent ID 0 1 2 3
10.1.15 CORE_AN_SENSE (O) This signal is tied to the Vcc seen at the processor core and represents the output of the OCVR. This signal provides the ability to monitor the stability of the OCVR in high reliability applications. The voltage seen at this pin is the actual operating voltage of the core with integrated L2 Cache minus IR drops due to trace routing in the Cartridge. 10.1.16 D[63:00]# (I/O) The D[63:00]# (Data) signals are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
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10.1.17 DBSY# (I/O) The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents. 10.1.18 DEFER# (I) The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of all processor system bus agents. 10.1.19 DEP[7:0]# (I/O) The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data bus. They are driven by the agent responsible for driving D[63:00]#, and must connect the appropriate pins of all processor system bus agents which use them. The DEP[7:0]# signals are enabled or disabled for ECC protection during power on configuration. 10.1.20 DRDY# (I/O) The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor system bus agents.
10.1.21 FERR# (O) The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel387TM coprocessor, and is included for compatibility with systems using DOStype floating-point error reporting. 10.1.22 FLUSH# (I) When the FLUSH# input signal is asserted, processors write back all data in the Modified state from their internal caches and invalidate all internal cache lines. At the completion of this operation, the processor issues a Flush Acknowledge transaction. The processor does not cache any new data while the FLUSH# signal remains asserted. FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction. On the active-to-inactive transition of RESET#, each processor samples FLUSH# to determine its power-on configuration. See Pentium II Processor Developer's Manual for details. 10.1.23 HIT# (I/O), HITM# (I/O) The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, and must connect the appropriate pins of all processor system bus agents. Any such agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. 10.1.24 HV_EN# (O) The HV_EN# signal is used as a way of differentiating a 5V/12V version processor cartridge from a 2.8V version. HV_EN# is tied to Vss (ground) on the 5V/12V version, and is high impedance (floating) on the 2.8V version. This is a reserved (no connect) pin on previous versions of the Pentium(R) III XeonTM processor. 10.1.25 IERR# (O) The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus. This transaction may optionally be converted to
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an external error signal (e.g. NMI) by system core logic. The processor will keep IERR# asserted until it is handled in software, or with the assertion of RESET#, BINIT#, or INIT#. 10.1.26 IGNNE# (I) The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction. During active RESET#, the processor begins sampling the A20M#, IGNNE# , and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See Table 1. On the active-to-inactive transition of RESET#, the processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals for normal operation.
10.1.27 INIT# (I) The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal (L1 or L2) caches or floating-point registers. Each processor then begins execution at the power-on reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-In Self-Test (BIST). 10.1.28 INTR - see LINT[0] 10.1.29 LINT[1:0] (I) The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium(R) processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the default configuration. During active RESET#, the Pentium(R) III XeonTM processor at 700 MHz begins sampling the A20M#, IGNNE#, and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency (See Table 1). On the active-toinactive transition of RESET#, the Pentium(R) III XeonTM processor at 700 MHz samples these signals and latches the frequency ratio internally. System logic must then release these signals for normal operation. The Pentium(R) III XeonTM processor at 900 MHz does not sample the A20M#, IGNNE#, and LINT[1:] values at the de-assertion of the RESET# signal, and will operate only with a 9:1 core/bus ratio. 10.1.30 LOCK# (I/O) The LOCK# signal indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all Pentium(R) III XeonTM processor at 700 MHz and 900 MHz system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz system bus throughout the bus locked operation and ensure the atomicity of lock.
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10.1.31 L2_SENSE On Pentium(R) III XeonTM processor at 500 MHz and 550 MHz cartridges, L2_SENSE is routed from the edge of the connector pin B57 to the VL2 power plane. It allows monitoring the delivery of Vcc_L2 voltage at the L2 array device for this processor. Since the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz does not have a separate L2 cache voltage supply, this line is NOT used and is not recommended to be connected in systems based on the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz only. Systems that rely on remote sensing of Vcc_L2 need to guarantee this requirement is met at the VRM sense line regardless of core feedback. 10.1.32 OCVR_EN (I) This signal is the output enable for the internal cartridge voltage regulator. Driving this Low will inactivate the outputs of the OCVR. This is an open drain signal referenced high to +5V through a 10K resistor within the cartridge to activate the VRM when not driven low (this to satisfy legacy requirements). Refer to Figure 41 and Figure 42 For PWRGD relationships at Power up.
10.1.33 OCVR_OK(O) This is an open drain compatible output from the On-Cartridge Voltage Regulator Module (OCVR) indicating that its outputs are enabled and operating within specifications. This signal is referenced to Vcc_SMB (+3.3V) through a 10K resistor, and should be used in conjunction with an equivalent signal from the host power system to generate the CORE_PWRGD signals for the processor cores. Refer to Figure 41 and Figure 42 for PWRGD relationships at Power up. PWRGD assertion must lag OCVR_OK assertion.
10.1.34 NMI - See LINT[1]
10.1.35 PICCLK (I) The PICCLK (APIC Clock) signal is a 2.5V tolerant input clock to the processor and core logic or I/O APIC that is required for operation of all processors, core logic, and I/O APIC components on the APIC bus. 10.1.36 PICD[1:0] (I/O) The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC bus, and must connect the appropriate pins of all processors and core logic or I/O APIC components on the APIC bus. 10.1.37 PRDY# (O) The PRDY (Probe Ready) signal is a processor output that is used by debug tools to determine processor debug readiness. 10.1.38 PREQ# (I) The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processors. 10.1.39 PWREN[1:0] (I) These 2 pins are tied directly together on the processor. They can be used to detect processor presence by applying a voltage to one pin and observing it at the other. See 3.9 for the maximum rating for this signal. 10.1.40 PWRGOOD (I) The (Power Good) signal is a 2.5V tolerant processor input. The processor requires this signal to be a clean indication that the clocks and power supplies (Vcc_CORE, VCC_L2, VCC_TAP, VCC_SMB, VCC2.5) are stable and within their
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specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on, until they come within specification. The signal must then transition monotonically to a high (2.5V) state. Figure 41 illustrates the relationship of PWRGD to other system signals. PWRGD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGD. It must also meet the minimum pulse width specification in Table 14 and be followed by a 8 mS RESET# pulse. The PWRGD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. Current VRM 8.3 (on baseboard) specification requires VRM_PWRGD to be asserted when its output is within 12% of nominal value. In the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz, PWRGD is logically ANDed with OCVR_OK before being applied to the core (PWRGD_CORE). According to legacy datasheet documents, RESET# negation is expected 1 mS after seeing PWRGD_CORE becoming valid by the processor core. The OCVR is not expected to provide a valid OCVR_OK signal assertion within 13 mS of seeing 90% of its input voltage. The delay before the assertion of OCVR_OK may cause a race condition between RESET# and the valid PWRGD_CORE that is seen at the core. It is recommended to relax the deassertion of RESET# to meet this critical constrain. Careful analysis needs to be done in existing platforms. Refer to Figure 41 and Figure 42 below for new timing relationship requirements.
1 3 mS RESE T#
VRM_ P WR G D OC VR_ O K
0 . mS (max ) 5
1 mS CPU_ P WR_ GD 2 .8 / / 2 V 51 Vin (O CV R) 9 0 %o f Vin No m in l a
VCC_ CPU
Vo ut (O CV R)
Figure 41. PWRGD Relationship at Power-On
NOTES:
1. 2. 3. 4. VCC_CORE must be applied to the OCVR input before OCVR_OK can become valid (even though it could be pulled high if the VCC_SMB supply is turned on, see figure 41. The OCVR_OK signal is not guaranteed to be valid until 0.5 mS (max) after Vin to the OCVR reaches 90% of it's nominal value. Vin is the input to the OCVR (VCC_CORE). Vout is the output from the OCVR (VCC_CPU).
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Pull-up for Pentium(R) III XeonTM Processor
3V->5V buffer (7408) 5V 3.3V +5V Vcc_smb(3.3V)
VRM OCVR_EN OUTEN PWRGD
OCVR OCVR_EN OCVR_OK
5V Other PS's, VRMs, OCVRs with open-drain PWR_GDs
PWR_GD_PS
3.3V
OCVR_OK CPU_PWRGD
CPU_PWR_GD
CPU_RESET#
Processor Core
Delay
Reset Logic
Figure 42. PWRGD Implementation
10.1.41 REQ[4:0]# (I/O) The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all processor system bus agents. They are asserted by the current bus owner over two clock cycles to define the currently active transaction type.
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10.1.42 RESET# (I) Asserting the RESET# signal resets all processors to known states and invalidates their L1 and L2 caches without writing back any of their contents. RESET# must remain active for one microsecond for a "warm" reset; for a power-on reset, RESET# must stay active for at least one millisecond after the PWRGOOD input to the processor has asserted; until this de-assertion of RESET# occurs, all outputs from the processor are indeterminate unless otherwise specified. On observing active RESET#, all processor system bus agents will de-assert their outputs within two clocks. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Pentium II Processor Developer's Manual. The processor may have its outputs tri-stated via power-on configuration. Otherwise, if INIT# is sampled active during the active-to-inactive transition of RESET#, the processor will execute its Built-In Self-Test (BIST). Whether or not BIST is executed, the processor will begin program execution at the reset-vector (default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of all processor system bus agents. 10.1.43 RP# (I/O) The RP# (Request Parity) signal is driven by the request initiator, and provides parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This definition allows parity to be high when all covered signals are high. 10.1.44 RS[2:0]# (I) The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. 10.1.45 RSP# (I) The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. 10.1.46 SA[2:0] (I) The SA (Select Address) pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors. To set an SA line high, a pull-up resistor should be used that is no larger than 1K. To set an SA line as low, the pin can be left unconnected. SA2 can also be tri-stated to define additional addresses for the thermal sensor. A tri-state or "Z" state on this pin is achieved by leaving this pin unconnected. Of the addresses broadcast across the SMBus, the memory components claim those of the form "1010XXYZb". The "XX" and "Y" bits are used to enable the devices on the cartridge at adjacent addresses. The Y bit is hard-wired on the cartridge to VSS (`0') for the Scratch EEPROM and pulled to VCCSMB (`1') for the processor Information ROM. The "XX" bits are defined by the processor slot via the SA0 and SA1 pins on the SC330 connector. These address pins are pulled down weakly (10 k ) on the cartridge to ensure that the memory components are in a known state in systems which do not support the SMBus, or only support a partial implementation. The "Z" bit is the read/write bit for the serial bus transaction. The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form "0011XXXZb", "1001XXXZb" or "0101XXXZb". The device's addressing, as implemented, includes a Hi-Z state for one address pin (SA2), and therefore supports 6 unique resulting addresses. The ability of the system to drive this pin to a Hi-Z state is dependent on the baseboard implementation (The pin must be left floating). The system should drive SA1 and SA0, and will be pulled low (if not driven) by the 10 k pull-down resistor on the processor substrate. Driving these signals to a Hi-Z state would cause ambiguity in the memory device address decode, possibly resulting in the devices not responding, thus timing out or hanging the SMBus. As before, the "Z" bit is the read/write bit for the serial bus transaction. For more information on the usage of these pins, see section 5.2.7.
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10.1.47 SELFSB0 (I) SELFSB1 (O) The Pentium(R) III XeonTM processor at 700 MHz and 900 MHz adds a definition to the SELFSB [1:0] pins which is compatible with legacy systems as well as new platforms. The added functionality provides the means for the clock synthesizer and additional baseboard logic to auto detect the expected system bus frequency required by a specific cartridge. Table 59 and Figure 43 provide a summary of the functionality and the resistor values for an frequency auto detect circuit.
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Table 59. Description of SELFSB pins
processor
Pentium(R) III XeonTM processor at 700 MHz and 900 MHz
Pin Location
A7
Pin Name
SELFSB1
Functionality
Output, Frequency Detect
A9
SELFSB0
Input, Frequency Selection.
Pentium(R) III XeonTM processor at 500 MHz and 550 MHz & Pentium(R) II XeonTM processor
A7 A9
Vss Reserved
None None
SELFSB1: Output, (Frequency Detect). 100 MHz = GND. SELFSB0:
Pentium(R) III XeonTM processor at 500 MHz and 550 MHz: Not used.. Pentium(R) III XeonTM processor at 700 MHz and 900 MHz: Input; (Frequency Select). 100 MHz= N/C or pull up to 2.5 V
2.5 V V a = 2.15 V 3.3 SE LF SB 1 C K 133 2.5 V 8.2 MC H 15 V c = 1.41 V 100M H z_SEL J umpers (f or debug onl y) 1 SE LF SB 0 9 7
Processo r Co re
Figure 43. Recommended circuit for frequency auto detection
10.1.48 SLP# (I) The SLP# (Sleep) signal, when asserted in Stop Grant state, causes processors to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop Grant state, restarting its internal clock signals to the bus and APIC processor core units. 10.1.49 SMBALERT# (O) SMBALERT# is an asynchronous interrupt line associated with the SMBus Thermal Sensor device. 10.1.50 SMBCLK (I)
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The SMBCLK (SMBus Clock) signal is an input clock to the system management logic which is required for operation of the system management features of the Pentium(R) III XeonTM processor at 700 MHz and 900 MHz. This clock is asynchronous to other clocks to the processor. 10.1.51 SMBDAT (I/O) The SMBDAT (SMBus DATA) signal is the data signal for the SMBus. This signal provides the single-bit mechanism for transferring data between SMBus devices. 10.1.52 SMI# (I) The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. 10.1.53 STPCLK# (I) The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop Grant state. The processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. 10.1.54 TCK (I) The TCK (Test Clock) signal provides the clock input for processor Test Bus (also known as the Test Access Port). 10.1.55 TDI (I) The TDI (Test Data In) signal transfers serial test data into the processor. TDI provides the serial input needed for TAP support. 10.1.56 TDO (O) The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO provides the serial output needed for TAP support. 10.1.57 TEST_2.5_[A23, A62, B27] (I) The TEST_2.5_A62 signal must be connected to a 2.5V power source through a 1-10K resistor for proper processor operation. 10.1.58 THERMTRIP# (O) This pin indicates a thermal overload condition (thermal trip). The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will immediately stop all execution when the junction temperature exceeds approximately 135C. This is signaled to the system by the THERMTRIP# pin. Once activated, the signal remains latched, and the processor stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself. Once the die temperature drops below the trip level, a RESET# pulse will reinitialize the processor and execution will continue at the reset vector. If the temperature has not dropped below the trip level, the processor will continue to drive THERMTRIP# and remain stopped regardless of the state of RESET#. The system designer should not act upon THERMTRIP# until after the RESET# input is de-asserted. Until this time, the THERMTRIP# output is indeterminate. 10.1.59 TMS (I) The TMS (Test Mode Select) signal is a TAP support signal used by debug tools.
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10.1.60 TRDY# (I) The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all processor system bus agents. 10.1.61 TRST# (I) The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The processor self-resets during power on; therefore, it is not necessary to drive this signal during power on reset. 10.1.62 VID_L2[4:0], VID_CORE[4:0] (O) The VID (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification variations on the processor. See Table 2 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself. See section 3.9 for the maximum rating for these signals. 10.1.63 VIN_SENSE VIN_SENSE (formerly called CPU_SENSE) is routed from edge-connector pin A56 to the VCC_CORE power plane. VIN_SENSE provides remote sensing capabilities for the voltage seen at the input of the OCVR. NOTE: Pentium(R) III XeonTM processor at 700 MHz and 900 MHz support either +2.8V, +5V or +12V VCC_CORE voltages depending on the version of OCVR. Therefore, any sensing logic must be capable of tolerating the selected VCC_CORE voltage (+2.8/+5V/+12V). 10.1.64 WP (I) WP (Write Protect) can be used to write protect the scratch EEPROM. A high level write-protects the scratch EEPROM.
10.2 Signal Summaries
The following tables list attributes of the processor input, output, and I/O signals.
Table 60. Output Signals Name FERR# IERR# PRDY# SMBALERT# TDO THERMTRIP# VID_CORE[4:0] VID_L2[4:0] CPU_SENSE L2_SENSE OCVR_OK Active Level Low Low Low Low High Low High High High High High Clock Asynch Asynch BCLK Asynch TCK Asynch Asynch Asynch Asynch Asynch Asynch Signal Group CMOS Output CMOS Output AGTL+ Output SMBus Output TAP Output CMOS Output Power/Other Power/Other Power/Other Power/Other Power/Other
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Table 61. Input Signals Name A20M# BPRI# BR[3:1]# BCLK DEFER# FLUSH# IGNNE# INIT# INTR LINT[1:0] NMI PICCLK PREQ# PWRGD RESET# RS[2:0]# RSP# SA[2:0] SMBCLK# SLP# SMI# STPCLK# TCK TDI TMS TRST# TRDY# WP OCVR_EN Active Level Low Low Low High Low Low Low Low High High High High Low High Low Low Low High High Low Low Low High High High Low Low High High Clock Asynch BCLK BCLK -- BCLK Asynch Asynch Asynch Asynch Asynch Asynch -- Asynch Asynch BCLK BCLK BCLK SMBCLK -- Asynch Asynch Asynch -- TCK TCK Asynch BCLK Asynch Asynch Signal Group CMOS Input AGTL+ Input AGTL+ Input System Bus Clock AGTL+ Input CMOS Input CMOS Input CMOS Input CMOS Input CMOS Input CMOS Input APIC Clock CMOS Input CMOS Input AGTL+ Input AGTL+ Input AGTL+ Input Power/Other SMBus Clock CMOS Input CMOS Input CMOS Input TAP Clock TAP Input TAP Input TAP Input AGTL+ Input SMBus Input Power/Other Always During Stop Grant state Qualified Always Always Always Always Always Always 2 Always 2 Always 2 APIC disabled mode APIC enabled mode APIC disabled mode Always Always Always Always Always Always
Table 62. I/O Signals (Single Driver) Name A[35:03]# ADS# AP[1:0]# SELFSB0 Active Level Low Low Low High Clock BCLK BCLK BCLK -- Signal Group AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other Qualified ADS#, ADS#+1 Always ADS#, ADS#+1
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Table 62. I/O Signals (Single Driver) Name SELFSB1 BR0# BP[3:2]# BPM[1:0]# D[63:00]# DBSY# DEP[7:0]# DRDY# LOCK# REQ[4:0]# RP# SMBDAT Active Level TBD Low Low Low Low Low Low Low Low Low Low High Clock TBD BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK SMBCLK Signal Group TBD AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O SMBus I/O Qualified TBD Always Always Always DRDY# Always DRDY# Always Always ADS#, ADS#+1 ADS#, ADS#+1
Table 63. I/O Signals (Multiple Driver) Name AERR# BERR# BNR# BINIT# HIT# HITM# PICD[1:0] Active Level Low Low Low Low Low Low High Clock BCLK BCLK BCLK BCLK BCLK BCLK PICCLK Signal Group AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O APIC I/O Qualified ADS#+3 Always Always Always Always Always Always
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